raster_sim: rewrite to fit new module definitions
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@ -2,6 +2,7 @@
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* must wrap "ram_fifo_dual_port" due to difficulties YOSYS has with
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* inferring Block RAM: refer to that module for details.
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*/
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`timescale 10ns/10ns
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module ram_fifo #(
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parameter DAT_WID = 24,
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parameter FIFO_DEPTH_WID = 11,
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@ -7,6 +7,7 @@
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* https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
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* The answer by "TinLethax" infers a BRAM.
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*/
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`timescale 10ns/10ns
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module ram_fifo_dual_port #(
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parameter DAT_WID = 24,
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parameter FIFO_DEPTH = 1500,
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@ -9,6 +9,7 @@
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* THIS MODULE ASSUMES that RAM_WORD < DAT_WID < RAM_WORD*2.
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*/
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`include "ram_shim_cmds.vh"
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`timescale 10ns/10ns
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module ram_shim #(
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parameter DAT_WID = 24,
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parameter RAM_WORD = 16,
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@ -6,6 +6,7 @@
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* over ethernet.
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*/
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`include "raster_cmds.vh"
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`timescale 10ns/10ns
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module raster #(
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parameter SAMPLEWID = 9,
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parameter DAC_DATA_WID = 20,
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@ -331,3 +332,4 @@ always @ (posedge clk) begin
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end
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endmodule
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`undefineall
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@ -1,4 +1,6 @@
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`timescale 10ns/10ns
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`include "raster_cmds.vh"
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`include "ram_shim_cmds.vh"
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module raster_sim #(
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parameter SAMPLEWID = 9,
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parameter DAC_DATA_WID = 20,
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@ -9,8 +11,6 @@ module raster_sim #(
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parameter ADCNUM = 9,
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parameter MAX_ADC_DATA_WID = 24,
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parameter BASE_ADDR = 32'h1000000,
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parameter MAX_BYTE_WID = 13,
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parameter DAT_WID = 24,
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parameter RAM_WORD = 16,
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parameter RAM_WID = 32,
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@ -19,46 +19,37 @@ module raster_sim #(
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parameter ADC_SIM_WAIT_TIME = 54
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) (
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input clk,
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input arm,
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output reg finished,
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output reg running,
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/* Amount of samples in one line (forward) */
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input [SAMPLEWID-1:0] max_samples_in,
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/* Amount of lines in the output. */
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input [SAMPLEWID-1:0] max_lines_in,
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/* Wait time after each step. */
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input [TIMER_WID-1:0] settle_time_in,
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input [`RASTER_CMD_WID-1:0] kernel_cmd,
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input [`RASTER_DATA_WID-1:0] kernel_data_in,
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output [`RASTER_DATA_WID-1:0] kernel_data_out,
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input kernel_ready,
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output kernel_finished,
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/* Each step goes (x,y) -> (x + dx, y + dy) forward for each line of
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* the output. */
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input signed [DAC_DATA_WID-1:0] dx_in,
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input signed [DAC_DATA_WID-1:0] dy_in,
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output [DAC_DATA_WID-1:0] x_dac,
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output [DAC_DATA_WID-1:0] y_dac,
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/* Vertical steps to go to the next line. */
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input signed [DAC_DATA_WID-1:0] dx_vert_in,
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input signed [DAC_DATA_WID-1:0] dy_vert_in,
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output reg [DAC_DATA_WID-1:0] coord_dac [1:0],
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/* Connections to all possible ADCs. These are connected to SPI masters
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* and they will automatically extend ADC value lengths to their highest
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* values. */
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output reg [ADCNUM-1:0] adc_arm,
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input [MAX_ADC_DATA_WID-1:0] adc_data [ADCNUM-1:0],
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input [ADCNUM-1:0] adc_finished,
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/* Bitmap for which ADCs are used. */
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input [ADCNUM-1:0] adc_used_in,
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/* DMA interface */
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output [RAM_WORD-1:0] word,
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output [RAM_WID-1:0] addr,
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output reg ram_write,
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input ram_valid
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input ram_valid,
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/* RAM shim control interface */
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input [RAM_WID-1:0] shim_cmd_data,
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input [`RAM_SHIM_CMD_WID-1:0] shim_cmd,
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input shim_cmd_active,
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output shim_cmd_finished,
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output [RAM_WID-1:0] shim_cmd_data_out
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);
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/**** DAC simulation ****/
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/**** DAC simulation.
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* The code to handle each axis (X and Y) are similar.
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****/
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reg [DAC_WID-1:0] coord_write_buf [1:0];
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reg [DAC_WID-1:0] coord_to_dac [1:0];
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@ -66,6 +57,10 @@ reg [DAC_WID-1:0] coord_from_dac [1:0];
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wire coord_arm [1:0];
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reg coord_finished [1:0];
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reg [DAC_DATA_WID-1:0] coord_dac [1:0];
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assign x_dac = coord_dac[0];
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assign y_dac = coord_dac[1];
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genvar ci;
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generate for (ci = 0; ci < 2; ci = ci + 1) begin
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initial begin
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@ -88,6 +83,7 @@ generate for (ci = 0; ci < 2; ci = ci + 1) begin
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coord_write_buf[ci] <= 0;
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coord_dac[ci] <= coord_from_dac[ci][DAC_WID-4-1:0];
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end
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default: ;
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endcase
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end else if (!coord_arm[ci]) begin
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@ -96,9 +92,13 @@ generate for (ci = 0; ci < 2; ci = ci + 1) begin
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end
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end endgenerate
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/**** ADC Shim ****/
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/**** ADC Shim
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* This shim and the shim below implement delays to simulate the actual
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* acquisition process. The values are then floated up to the Verilator
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* simulator so the C++ code doesn't have to implement timers manually.
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****/
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wire adc_arm_internal;
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wire [ADCNUM-1:0] adc_arm_internal;
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reg [31:0] adc_wait_cntr = 0;
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always @ (posedge clk) begin
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@ -115,51 +115,53 @@ end
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/**** RAM Shim ****/
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/* Check all addresses are valid. */
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property address_in_range;
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@(posedge clk)
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ram_commit |->
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BASE_ADDR <= addr && addr < BASE_ADDR + (1 << MAX_BYTE_WID);
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endproperty
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address_in_range_assert: assert property (address_in_range);
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wire signed [DAT_WID-1:0] ram_data;
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wire ram_commit;
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wire ram_write_finished;
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wire ram_write_internal = 0;
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reg [31:0] ram_cntr = 0;
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wire ram_write_internal;
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reg [31:0] ram_wait_cntr = 0;
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always @ (posedge clk) begin
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if (ram_commit) begin
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if (ram_cntr < RAM_SIM_WAIT_TIME) begin
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ram_cntr <= ram_cntr + 1;
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if (!ram_write_internal) begin
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ram_wait_cntr <= 0;
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end else if (ram_wait_cntr < RAM_SIM_WAIT_TIME) begin
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ram_wait_cntr <= ram_wait_cntr + 1;
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end else begin
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ram_write <= 1;
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end
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end else begin
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ram_cntr <= 0;
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ram_write <= 0;
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end
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end
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wire [MAX_ADC_DATA_WID-1:0] ram_data;
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wire ram_commit;
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wire ram_finished;
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ram_shim #(
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.BASE_ADDR(BASE_ADDR),
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.MAX_BYTE_WID(MAX_BYTE_WID),
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.DAT_WID(DAT_WID),
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.RAM_WORD(RAM_WORD),
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.RAM_WID(RAM_WID)
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) ram (
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.clk(clk),
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.rst(0),
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.data(ram_data),
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.commit(ram_commit),
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.finished(ram_write_finished),
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.data_commit(ram_commit),
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.finished(ram_finished),
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.word(word),
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.addr(addr),
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.write(ram_write_internal),
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.valid(ram_valid)
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.valid(ram_valid),
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.cmd_data(shim_cmd_data),
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.cmd(shim_cmd),
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.cmd_active(shim_cmd_active),
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.cmd_finished(shim_cmd_finished),
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.cmd_data_out(shim_cmd_data_out)
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);
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/* Converting array to vector, arrays are easier to handle in Verilator. */
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wire [ADCNUM*MAX_ADC_DATA_WID-1:0] adc_data_internal;
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genvar ii;
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generate for (ii = 0; ii < ADCNUM; ii = ii + 1) begin
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assign adc_data_internal[(ii+1)*MAX_ADC_DATA_WID-1:ii*MAX_ADC_DATA_WID]
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= adc_data[ii];
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end endgenerate
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raster #(
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.SAMPLEWID(SAMPLEWID),
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.DAC_DATA_WID(DAC_DATA_WID),
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@ -170,37 +172,31 @@ raster #(
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.MAX_ADC_DATA_WID(MAX_ADC_DATA_WID)
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) raster (
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.clk(clk),
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.arm(arm),
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.finished(finished),
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.running(running),
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.steps_per_sample_in(steps_per_sample_in),
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.max_samples_in(max_samples_in),
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.max_lines_in(max_lines_in),
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.settle_time_in(settle_time_in),
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.dx_in(dx_in),
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.dy_in(dy_in),
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.dx_vert_in(dx_vert_in),
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.dy_vert_in(dy_vert_in),
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.x_arm(x_arm),
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.x_to_dac(x_to_dac),
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.x_from_dac(x_from_dac),
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.x_finished(x_finished),
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.kernel_cmd(kernel_cmd),
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.kernel_data_in(kernel_data_in),
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.kernel_data_out(kernel_data_out),
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.kernel_ready(kernel_ready),
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.kernel_finished(kernel_finished),
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.y_arm(y_arm),
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.y_to_dac(y_to_dac),
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.y_from_dac(y_from_dac),
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.y_finished(y_finished),
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.x_arm(coord_arm[0]),
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.x_to_dac(coord_to_dac[0]),
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.x_from_dac(coord_from_dac[0]),
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.x_finished(coord_finished[0]),
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.y_arm(coord_arm[1]),
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.y_to_dac(coord_to_dac[1]),
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.y_from_dac(coord_from_dac[1]),
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.y_finished(coord_finished[1]),
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.adc_arm(adc_arm_internal),
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.adc_data(adc_data),
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.adc_data(adc_data_internal),
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.adc_finished(adc_finished),
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.adc_used_in(adc_used_in),
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.data(ram_data),
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.mem_commit(ram_commit),
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.mem_finished(ram_write_finished)
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.mem_finished(ram_finished)
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);
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endmodule
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`undefineall
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