some more changes
This commit is contained in:
parent
5125719a1f
commit
029cc53c5f
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@ -0,0 +1,64 @@
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# Functions for converting to and from fixed point in Python.
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from math import log10, floor
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def string_to_fixed_point(s, fracnum):
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l = s.split('.')
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if len(l) == 1:
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return int(s) << fracnum
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elif len(l) != 2:
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return None
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dec = 10
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frac = 0
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frac_decimal = int(l[1])
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# get the smallest power of ten higher then frac_decimal
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frac_decimal_len = floor(log10(frac_decimal) + 1)
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pow10 = 10**frac_decimal_len
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frac = 0
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# Example:
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# 0.4567 = 0.abcdefgh...
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# where abcdefgh are binary digits.
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# multiply both sides by two:
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# 0.9134 = a.bcdefgh ...
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# therefore a = 0. Then remove the most significant digit.
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# Then multiply by 2 again. Then
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# 18268 = b.cdefgh ...
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# therefore b = 1. Then take 8268, and so on.
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for i in range(0,fracnum):
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frac_decimal = frac_decimal * 2
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div, mod = divmod(frac_decimal, pow10)
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frac = div | (frac << 1)
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frac_decimal = mod
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whole = int(l[0])
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if whole < 0:
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return -((-whole) << fracnum | frac)
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else:
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return whole << fracnum | frac
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def fixed_point_to_string(fxp, fracnum):
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whole = str(fxp >> fracnum)
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mask = (1 << fracnum) - 1
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fracbit = fxp & mask
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n = 1
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frac = ""
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if fracbit == 0:
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return whole
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# The same method can be applied backwards.
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# 0.1110101 = 0.abcdefgh ...
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# where abcdefgh... are decimal digits. Then multiply by 10 to
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# get
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# 1001.0010010 = a.bcdefgh ...
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# therefore a = 0b1001 = 9. Then use a bitmask to get
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# 0.0010010 = 0.bcdefgh ...
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# etc.
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for i in range(0, fracnum):
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fracbit = fracbit * 10
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frac = frac + str(fracbit >> fracnum)
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fracbit = fracbit & mask
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return whole + "." + frac
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@ -1,3 +1,5 @@
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/* TODO: move SPI masters out of the control loop design */
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/************ Introduction to PI Controllers
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* The continuous form of a PI loop is
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*
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@ -129,16 +131,17 @@ module control_loop
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output adc_sck,
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input adc_in,
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output adc_conv,
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output adc_conv, // active high
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output dac_sck,
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output dac_ss,
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output dac_ss, // active high
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output dac_out,
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/* Informational output.
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* These registers are also used for storing information while
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* the loop is running.
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*/
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output signed [ERR_WID-1:0] err_cur,
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output signed [CONSTS_WID-1:0] adj,
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@ -375,20 +378,24 @@ always @ (posedge clk) begin
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state <= WAIT_ON_ADC;
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timer <= 0;
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adc_arm <= 1;
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adc_conv <= 1;
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end
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end
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WAIT_ON_ADC: if (adc_finished) begin
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adc_arm <= 0;
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adc_conv <= 0;
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arm_mul <= 1;
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state <= WAIT_ON_MUL;
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end
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WAIT_ON_MUL: if (mul_finished) begin
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arm_mul <= 0;
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dac_arm <= 1;
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dac_ss <= 1;
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state <= WAIT_ON_DAC;
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end
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WAIT_ON_DAC: if (dac_finished) begin
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state <= WAIT_ON_ARM;
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dac_ss <= 0;
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dac_arm <= 0;
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end
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end
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@ -1,8 +1,11 @@
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#include <memory>
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#include <limits>
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#include <cstdint>
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#include <cstring>
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#include <cstdlib>
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#include <iostream>
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#include <random>
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#include <unistd.h>
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#include <verilated.h>
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#include "Vcontrol_loop.h"
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@ -19,21 +22,190 @@ Vcontrol_loop *mod;
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*/
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class Transfer {
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std::random_device rd;
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std::default_random_engine generator;
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std::normal_distribution dist;
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double scale;
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double sample() {return scale*dist(rd);}
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public:
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Transfer(double scale, double mean, double dev, double m, double b)
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: scale{scale}, rd{}, dist{mean,dev} {}
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Transfer(double scale, double mean, double dev, double m, double b, int seed)
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: scale{scale}, dist{mean,dev}, generator{} {
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if (seed < 0) {
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std::random_device rd;
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generator.seed(rd());
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} else {
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generator.seed(seed);
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}
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}
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double val(double x) {
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return m*x + b + sample();
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}
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};
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int main(int argc, char **argv) {
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/* Each constant is 48 bits long, with 15 whole bits.
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constexpr auto CONSTS_WHOLE_WID = 15;
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constexpr auto CONSTS_WID = 48;
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constexpr auto CONSTS_FRAC_WID = CONSTS_WID - CONSTS_WHOLE_WID;
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constexpr auto CONSTS_FRAC_MASK = (1 << CONSTS_FRAC_WID) - 1;
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constexpr uint64_t fractional_base_conv(uint64_t input) {
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/* Fractional base conversion algorithm.
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Given an integer in base M (i.e. 10) there is an expansion in base N (i.e. 2):
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0.abcdefgh... = 0.ijklmnop...
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where abcdefgh... are in base M and ijklmnop... are in base N. The algorithm
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computes the digits in base N.
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Multiply the converted number by N. Then there are new numbers:
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A.BCDEFGH... = i.jklmnop...
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Since 0.abcdefgh < 1, A.BCDEFGH < N. Therefore
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the digit "A" must be a number less than N. Then i = A. Cutting off all the
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other digits,
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0.BCDEFGH... = 0.jklmnop...
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continue until there are no more digits left.
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*/
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/* Calculate the lowest power of 10 greater than input.
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This can be done with logarithms, but floating point is not available on
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some embedded platforms. This makes the code more portable.
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*/
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uint64_t pow10 = 1;
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while (input / pow10 > 0)
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pow10 *= 10;
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uint64_t out = 0;
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for (unsigned i = 0; i < CONSTS_FRAC_WID; i++) {
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input *= 2;
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uint64_t dig = input / pow10, mod = input % pow10;
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out = dig | (out << 1);
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input = mod;
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}
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return out;
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}
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static int64_t multiply_unity(uint64_t i, int sign) {
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if (sign > 0) {
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return std::reinterpret_cast<int64_t>(i);
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} else {
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return std::reinterpret_cast<int64_t>(~i + 1);
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}
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}
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constexpr uint64_t SCALE_WHOLE = 12820;
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constexpr uint64_t SCALE_FRAC = fractional_base_conv(51282051282);
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constexpr uint64_t SCALE_NUM = (SCALE_WHOLE << CONSTS_FRAC_WID) | SCALE_FRAC;
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static int64_t signed_to_fxp(char *s) {
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// Skip whitespace.
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while (isspace(*c++));
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// Check if number is negative.
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int sign = 1;
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if (*s == '-') {
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pos = -1;
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s++;
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}
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// Split the number into whole and fractional components.
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char *p = strchr(s, '.');
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if (!p)
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return multiply_unity(strtoull(s, NULL, 10), sign);
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*p = 0;
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// s now points to a NUL terminated string with the whole number
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// component.
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uint64_t whole = strtoull(s, NULL, 10);
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p++;
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// p is the start of the fractional component.
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uint64_t frac_decimal = strtoull(p, NULL, 10);
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uint64_t final = ((whole << CONSTS_FRAC_WID) | fractional_base_conv(frac_decimal, CONSTS_FRAC_WID))
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* SCALE_NUM;
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return multiply_unity(final, sign);
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}
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static std::string fxp_to_str(int64_t inum, unsigned decdigs) {
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std::string s = "";
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uint64_t num;
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if (inum < 0) {
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num = std::reinterpret_cast<uint64_t>(~inum) + 1;
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s.insert(0,1, '-');
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} else {
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num = std::reinterpet_cast<uint64_t>(num);
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}
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s += std::to_string(num >> CONSTS_FRAC_WID);
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int64_t frac = num & CONSTS_FRAC_MASK;
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if (frac == 0 || decdigs == 0)
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return;
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s += ".";
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/* Applying the algorithm in fractional_base_conv() backwards. */
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while (decdigs > 0 && frac != 0) {
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num *= 2;
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s += std::to_string(num >> CONSTS_FRAC_WID);
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num = num & CONSTS_FRAC_WID;
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}
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return s;
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}
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static int64_t I_const, dt_const, P_const, setpt;
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static unsigned long seed, ;
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static void usage(char *argv0, int code) {
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std::cout << argv0 << " -I I -t dt -d delay -s seed -S setpt -P p [+verilator...]" << std::endl;
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exit(code);
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}
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static void parse_args(int argc, char *argv[]) {
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const char *optstring = "I:t:s:P:h";
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int opt;
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Verilated::commandArgs(argc, argv);
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while ((opt = getopt(argc, argv, optstring)) != -1) {
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switch (opt) {
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case 'I':
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I_const = signed_to_fxp(optarg);
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break;
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case 't':
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dt_const = signed_to_fxp(optarg);
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break;
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case 'S':
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setpt = signed_to_fxp(optarg);
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break;
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case 's':
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seed = strtoul(optarg, NULL, 10);
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break;
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case 'P':
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P_const = strtoul(optarg, NULL, 10);
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break;
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case 'd':
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dely = strtoul(optarg, NULL, 10);
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break;
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case 'h':
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usage(argv[0], 0);
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break;
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default:
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usage(argv[1], 1);
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break;
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}
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}
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}
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Vtop *mod;
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int main(int argc, char **argv) {
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parse_args(argc, argv);
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mod = new Vtop;
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mod->clk = 0;
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mod->arm = 1;
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mod->setpt = setpt;
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mod->alpha = I_const * dt_const + P_const;
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mod->cl_p = P_const;
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mod->dy = 5;
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}
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@ -7,10 +7,12 @@ module top
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parameter DAC_DATA_WID = 20,
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parameter CONSTS_WID = 48,
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parameter DELAY_WID = 16
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(
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)(
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input clk,
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input signed [ADC_WID-1:0] read_data,
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output signed [DAC_WID-1:0] write_data,
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input arm,
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input signed [ADC_WID-1:0] measured_data,
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output signed [DAC_WID-1:0] output_data,
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input signed [ADC_WID-1:0] setpt,
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input signed [CONSTS_WID-1:0] alpha,
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input signed [CONSTS_WID-1:0] cl_p,
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@ -22,21 +24,79 @@ module top
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wire adc_sck;
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wire adc_ss;
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wire adc_mosi;
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wire adc_miso;
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reg adc_finished = 0;
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wire dac_mosi;
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wire dac_sck;
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wire dac_ss;
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reg dac_finished = 0;
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/* Emulate a control loop environment with simulator controlled
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SPI interfaces.
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*/
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/* ADC */
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spi_slave_no_write #(
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.WID(ADC_WID),
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.WID(5),
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.
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.WID_LEN(5),
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.ADC_POLARITY(ADC_POLARITY),
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.ADC_PHASE(ADC_PHASE)
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)(
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.clk(clk),
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.to_master(measured_data),
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.sck(adc_sck),
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.ss_L(!adc_ss),
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.miso(adc_miso),
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.rdy(!dac_ss),
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.finished(adc_finished)
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);
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/* DAC */
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spi_slave_no_read #(
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.WID(DAC_WID),
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.WID_LEN(5),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE)
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)(
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.clk(clk),
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.from_master(output_data),
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.mosi(dac_mosi),
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.sck(dac_sck),
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.ss_L(!dac_ss),
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.rdy(!dac_ss),
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.finished(dac_finished)
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);
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control_loop #(
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.ADC_WID(ADC_WID),
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.DAC_WID(DAC_WID),
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.DAC_DATA_WID(DAC_DATA_WID),
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.CONSTS_WID(CONSTS_WID),
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.DELAY_WID(DELAY_WID)
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.DELAY_WID(DELAY_WID),
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.ADC_POLARITY(ADC_POLARITY),
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.ADC_PHASE(ADC_PHASE),
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.DAC_POLARITY(DAC_POLARITY),
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.DAC_PHASE(DAC_PHASE)
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) cloop (
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.clk(clk),
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.arm(arm),
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.adc_sck(adc_sck),
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.adc_in(adc_miso),
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.adc_conv(adc_ss),
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.dac_sck(dac_sck),
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.dac_ss(dac_ss),
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.dac_out(dac_mosi),
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.setpt_in(setpt),
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.cl_alpha_in(alpha),
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.cl_p_in(cl),
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.delay_in(dy),
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.err(err_cur),
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.adj(adj)
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);
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endmodule
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@ -0,0 +1,101 @@
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module raster #(
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parameter SAMPLEWID = 9,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID = 24,
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parameter STEPWID = 16,
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parameter MAX_ADC_DATA_WID = 24
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) (
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input clk,
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input arm,
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/* Amount of steps per sample. */
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input [STEPWID-1:0] steps,
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/* Amount of samples in one line (forward) */
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input [SAMPLEWID-1:0] samples,
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/* Amount of lines in the output. */
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input [SAMPLEWID-1:0] lines,
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/* Each step goes (x,y) -> (dx,dy) forward for each line of
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* the output. */
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input signed [DAC_DATA_WID-1:0] dx,
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input signed [DAC_DATA_WID-1:0] dy,
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/* Vertical steps to go to the next line. */
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input signed [DAC_DATA_WID-1:0] dx_vert,
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input signed [DAC_DATA_WID-1:0] dy_vert,
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/* X and Y DAC piezos */
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input x_ready,
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output [DACWID-1:0] x_to_dac,
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input [DACWID-1:0] x_from_dac,
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output x_finished,
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input y_ready,
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output [DACWID-1:0] y_to_dac,
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input [DACWID-1:0] y_from_dac,
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output y_finished,
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/* Connections to all possible ADCs. These are connected to SPI masters
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* and they will automatically extend ADC value lengths to their highest
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* values. */
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input adc_in [0:ADCNUM-1],
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output [MAX_ADC_DATA_WID-1:0] adc_conv [0:ADCNUM-1],
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output adc_finished [0:ADCNUM-1],
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/* Bitmap for which ADCs are used. */
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input [ADCNUM-1:0] adc_used,
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output signed [MAX_ADC_DATA_WID-1:0] fifo_data,
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output fifo_ready,
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input fifo_valid
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);
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/* State machine:
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┏━━━━ WAIT ON ARM
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↑ ↓ (arm -> 1)
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┃ GET DAC VALUES
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┃ ↓ (when x and y values are obtained)
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┃ ┏━LOOP FORWARD WITHOUT MEASUREMENT
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┃ ↑ ↓ (when enough steps are taken)
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┃ ┃ GET ADC VALUES
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||||
┃ ┃ ↓ (when all ADC values are obtained)
|
||||
┃ ┃ SEND THROUGH FIFO
|
||||
┃ ┃ ↓ (when finished)
|
||||
┃ ┏━┫ ┃
|
||||
┃ ↑ ┗━━━←━┫
|
||||
┃ ┃ ┃ (when at the end of a line)
|
||||
┃ ┃ ┃
|
||||
┃ ┃ ┏━LOOP BACKWARD WITHOUT MEASUREMENT
|
||||
┃ ┃ ↑ ↓ (when enough steps are taken)
|
||||
┃ ┃ ┃ GET ADC VALUES, BACKWARDS MEASUREMENT
|
||||
┃ ┃ ┃ ↓ (when all ADC values are obtained)
|
||||
┃ ┃ ┃ SEND THROUGH FIFO, BACKWARDS MEASUREMENT
|
||||
┃ ┃ ┃ ↓ (when finished)
|
||||
┃ ┃ ┃ ┃
|
||||
┃ ┃ ┗━━━←━┫
|
||||
┃ ┃ ↓
|
||||
┃ ┗━━━━━━━┫
|
||||
┃ ↓ (when the image is finished)
|
||||
┃ ┃
|
||||
┃ WAIT FOR ARM DEASSERT
|
||||
┃ ↓ (when arm = 0)
|
||||
┗━━━━━━━━━┛
|
||||
*/
|
||||
|
||||
localparam WAIT_ON_ARM = 0;
|
||||
localparam GET_DAC_VALUES = 1;
|
||||
localparam INCREMENT_XVAL = 2;
|
||||
localparam GET_ADC_VAL = 3;
|
||||
localparam SEND_FIFO = 4;
|
||||
localparam WAIT_FOR_REARM = 5;
|
||||
|
||||
reg [2:0] stepstate = WAIT_ON_ARM;
|
||||
reg is_forward = 1;
|
||||
reg [SAMPLEWID-1:0] samplenum;
|
||||
reg [STEPWID-1:0] stepnum;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
module sign_extend #(
|
||||
parameter WID1 = 18,
|
||||
parameter WID2 = 24
|
||||
) (
|
||||
input signed [WID1-1:0] b1,
|
||||
output signed [WID2-1:0] b2
|
||||
);
|
||||
|
||||
assign b2[WID1-1:0] = b1;
|
||||
/* Assign the high bits of b2 to be the extension of the
|
||||
* highest bit of b1. If the MSB of b1 is 1 (i.e. b1 is
|
||||
* negative), then all high bits of b2 must be negative.
|
||||
* If the MSB of b1 is 0, then the high bits of b2 must
|
||||
* be zero.
|
||||
*/
|
||||
assign b2[WID2-1:WID1] = {(WID2-WID1){b1[WID1-1]}};
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/* (c) Peter McGoron 2022 v0.1
|
||||
* This Source Code Form is subject to the terms of the Mozilla Public
|
||||
* License, v.2.0. If a copy of the MPL was not distributed with this
|
||||
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
|
||||
*/
|
||||
|
||||
module
|
||||
`ifdef SPI_SLAVE_NO_READ
|
||||
spi_slave_no_read
|
||||
`elsif SPI_SLAVE_NO_WRITE
|
||||
spi_slave_no_write
|
||||
`else
|
||||
spi_slave
|
||||
`endif
|
||||
#(
|
||||
parameter WID = 24, // Width of bits per transaction.
|
||||
parameter WID_LEN = 5, // Length in bits required to store WID
|
||||
parameter POLARITY = 0,
|
||||
parameter PHASE = 0 // 0 = rising-read falling-write, 1 = rising-write falling-read.
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input sck,
|
||||
input ss_L,
|
||||
`ifndef SPI_SLAVE_NO_READ
|
||||
output reg [WID-1:0] from_master,
|
||||
input reg mosi,
|
||||
`endif
|
||||
`ifndef SPI_SLAVE_NO_WRITE
|
||||
input [WID-1:0] to_master,
|
||||
output reg miso,
|
||||
`endif
|
||||
output reg finished,
|
||||
input rdy,
|
||||
output reg err
|
||||
);
|
||||
|
||||
wire ss = !ss_L;
|
||||
reg sck_delay = 0;
|
||||
reg [WID_LEN-1:0] bit_counter = 0;
|
||||
reg ss_delay = 0;
|
||||
reg ready_at_start = 0;
|
||||
|
||||
`ifndef SPI_SLAVE_NO_WRITE
|
||||
reg [WID-1:0] send_buf = 0;
|
||||
`endif
|
||||
|
||||
task read_data();
|
||||
`ifndef SPI_SLAVE_NO_READ
|
||||
from_master <= from_master << 1;
|
||||
from_master[0] <= mosi;
|
||||
`endif
|
||||
endtask
|
||||
|
||||
task write_data();
|
||||
`ifndef SPI_SLAVE_NO_WRITE
|
||||
send_buf <= send_buf << 1;
|
||||
miso <= send_buf[WID-1];
|
||||
`endif
|
||||
endtask
|
||||
|
||||
task setup_bits();
|
||||
`ifndef SPI_SLAVE_NO_WRITE
|
||||
/* at Mode 00, the transmission starts with
|
||||
* a rising edge, and at mode 11, it starts with a falling
|
||||
* edge. For both modes, these are READs.
|
||||
*
|
||||
* For mode 01 and mode 10, the first action is a WRITE.
|
||||
*/
|
||||
if (POLARITY == PHASE) begin
|
||||
miso <= to_master[WID-1];
|
||||
send_buf <= to_master << 1;
|
||||
end else begin
|
||||
send_buf <= to_master;
|
||||
end
|
||||
`endif
|
||||
endtask
|
||||
|
||||
task check_counter();
|
||||
if (bit_counter == WID) begin
|
||||
err <= ready_at_start;
|
||||
end else begin
|
||||
bit_counter <= bit_counter + 1;
|
||||
end
|
||||
endtask
|
||||
|
||||
always @ (posedge clk) begin
|
||||
sck_delay <= sck;
|
||||
ss_delay <= ss;
|
||||
|
||||
case ({ss_delay, ss})
|
||||
2'b01: begin // rising edge of SS
|
||||
bit_counter <= 0;
|
||||
finished <= 0;
|
||||
err <= 0;
|
||||
ready_at_start <= rdy;
|
||||
|
||||
setup_bits();
|
||||
end
|
||||
2'b10: begin // falling edge
|
||||
finished <= ready_at_start;
|
||||
end
|
||||
2'b11: begin
|
||||
case ({sck_delay, sck})
|
||||
2'b01: begin // rising edge
|
||||
if (PHASE == 1) begin
|
||||
write_data();
|
||||
end else begin
|
||||
read_data();
|
||||
end
|
||||
|
||||
if (POLARITY == 0) begin
|
||||
check_counter();
|
||||
end
|
||||
end
|
||||
2'b10: begin // falling edge
|
||||
if (PHASE == 1) begin
|
||||
read_data();
|
||||
end else begin
|
||||
write_data();
|
||||
end
|
||||
|
||||
if (POLARITY == 1) begin
|
||||
check_counter();
|
||||
end
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
2'b00: if (!rdy) begin
|
||||
finished <= 0;
|
||||
err <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
`define SPI_SLAVE_NO_WRITE
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
`include "spi_slave.v"
|
||||
Loading…
Reference in New Issue