autoapproach: add bram and test
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034f76da41
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@ -0,0 +1,19 @@
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# Makefile for tests and hardware verification.
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.PHONY: test clean
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test: obj_dir/Vbram_interface
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bram_SRC= bram_interface.v bram_interface_sim.cpp
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obj_dir/Vbram_interface.mk: $(bram_SRC)
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verilator --cc --exe -Wall --trace --trace-fst \
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-CFLAGS -DWORD_AMNT=2048 \
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-CFLAGS -DRAM_WID=32 \
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$(bram_SRC)
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obj_dir/Vbram_interface: obj_dir/Vbram_interface.mk
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cd obj_dir && make -f Vbram_interface.mk
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./obj_dir/Vbram_interface
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clean:
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rm -rf obj_dir/
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@ -1,9 +1,12 @@
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/* Autoapproach module. This module applies a waveform located in memory
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* (and copied into Block RAM). This waveform is arbitrary but of fixed
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* length.
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* time in between sent sample, total period 10-50ms
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*/
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module autoapproach #(
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parameter DAC_WID = 24
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 24
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) (
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input clk,
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input arm,
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@ -11,13 +14,13 @@ module autoapproach #(
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output detected,
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input polarity,
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input [`ADC_WID-1:0] setpoint,
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input [ADC_WID-1:0] setpoint,
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/* BRAM memory interface. Each pulse returns the next value in
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* the sequence, and also informs the module if the sequence
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* is completed. The kernel interacts primarily with this interface.
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*/
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input [`DAC_DATA_WID-1:0] word,
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input [DAC_DATA_WID-1:0] word,
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output word_next,
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input word_last,
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input word_ok,
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@ -26,12 +29,12 @@ module autoapproach #(
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/* DAC wires. */
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input dac_finished,
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output dac_arm,
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input [`DAC_WID-1:0] dac_in,
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output [`DAC_WID-1:0] dac_out,
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input [DAC_WID-1:0] dac_in,
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output [DAC_WID-1:0] dac_out,
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input adc_finished,
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output adc_arm,
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input [`ADC_WID-1:0] measurement
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input [ADC_WID-1:0] measurement
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);
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@ -41,7 +44,6 @@ localparam WAIT_ON_DAC = 2;
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localparam WAIT_ON_DETECTION = 3;
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localparam DETECTED = 4;
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reg [2:0] state = WAIT_ON_ARM;
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reg save_word_last = 0;
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always @ (posedge clk) case (state)
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WAIT_ON_ARM: if (arm) begin
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@ -55,25 +57,25 @@ end
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RECV_WORD: if (word_ok) begin
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dac_out <= {4'b0001, word};
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dac_arm <= 1;
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save_word_last <= word_last;
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word_next <= 0;
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state <= WAIT_ON_DAC;
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end
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WAIT_ON_DAC: if (dac_finished) begin
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dac_arm <= 0;
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if (save_word_last) begin
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/* Was the last word read *the* last word? */
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if (word_last) begin
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state <= WAIT_ON_DETECTION;
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adc_arm <= 0;
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adc_arm <= 1;
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end else begin
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state <= WAIT_ON_ARM;
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end
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endcase
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WAIT_ON_DETECTION: if (adc_finished) begin
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if (polarity && measurement >= setpt) begin
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if ((polarity && measurement >= setpt) ||
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(!polarity && measurement <= setpt)) begin
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state <= DETECTED;
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detected <= 1;
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end else if (measurement <= setpt) begin
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state <= WAIT_ON_ARM;
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end
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end
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DETECTED: if (!arm) begin
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@ -0,0 +1,112 @@
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module bram_interface #(
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parameter WORD_WID = 24,
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parameter WORD_AMNT_WID = 11,
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/* This is the last INDEX, not the LENGTH of the word array. */
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parameter [WORD_AMNT_WID-1:0] WORD_AMNT = 2047,
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parameter RAM_WID = 32,
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parameter RAM_WORD_WID = 16,
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parameter RAM_WORD_INCR = 2
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) (
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input clk,
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/* autoapproach interface */
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output reg [WORD_WID-1:0] word,
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input word_next,
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output reg word_last,
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output reg word_ok,
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input word_rst,
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/* User interface */
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input refresh_start,
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input [RAM_WID-1:0] start_addr,
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output reg refresh_finished,
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/* RAM interface */
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output reg [RAM_WID-1:0] ram_dma_addr,
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input [RAM_WORD_WID-1:0] ram_word,
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output reg ram_read,
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input ram_valid
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);
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initial word = 0;
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initial word_last = 0;
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initial word_ok = 0;
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initial refresh_finished = 0;
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initial ram_dma_addr = 0;
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initial ram_read = 0;
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reg [WORD_WID-1:0] backing_buffer [WORD_AMNT:0];
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localparam WAIT_ON_REFRESH = 0;
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localparam READ_LOW_WORD = 1;
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localparam READ_HIGH_WORD = 2;
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localparam WAIT_ON_REFRESH_DEASSERT = 3;
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reg [1:0] refresh_state = 0;
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reg [WORD_AMNT_WID-1:0] word_cntr_refresh = 0;
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always @ (posedge clk) case (refresh_state)
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WAIT_ON_REFRESH: if (refresh_start) begin
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ram_dma_addr <= start_addr;
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refresh_state <= READ_LOW_WORD;
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word_cntr_refresh <= 0;
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end
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READ_LOW_WORD: if (!ram_read) begin
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ram_read <= 1;
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end else if (ram_valid) begin
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refresh_state <= READ_HIGH_WORD;
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ram_dma_addr <= ram_dma_addr + RAM_WORD_INCR;
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ram_read <= 0;
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backing_buffer[word_cntr_refresh][RAM_WORD_WID-1:0] <= ram_word;
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end
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READ_HIGH_WORD: if (!ram_read) begin
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ram_read <= 1;
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end else if (ram_valid) begin
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ram_dma_addr <= ram_dma_addr + RAM_WORD_INCR;
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ram_read <= 0;
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word_cntr_refresh <= word_cntr_refresh + 1;
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backing_buffer[word_cntr_refresh][WORD_WID-1:RAM_WORD_WID] <= ram_word[WORD_WID-RAM_WORD_WID-1:0];
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if (word_cntr_refresh == WORD_AMNT)
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refresh_state <= WAIT_ON_REFRESH_DEASSERT;
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else
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refresh_state <= READ_LOW_WORD;
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end
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WAIT_ON_REFRESH_DEASSERT: begin
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if (!refresh_start) begin
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refresh_finished <= 0;
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refresh_state <= WAIT_ON_REFRESH;
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end else begin
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refresh_finished <= 1;
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end
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end
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endcase
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reg [WORD_AMNT_WID-1:0] auto_cntr = 0;
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always @ (posedge clk) if (word_rst) begin
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auto_cntr <= 0;
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end else if (word_next && !word_ok) begin
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if (refresh_state == WAIT_ON_REFRESH) begin
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word <= backing_buffer[auto_cntr];
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word_ok <= 1;
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if (auto_cntr == WORD_AMNT) begin
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auto_cntr <= 0;
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word_last <= 1;
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end else begin
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auto_cntr <= auto_cntr + 1;
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word_last <= 0;
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end
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end
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end else if (!word_next && word_ok) begin
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word_ok <= 0;
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end
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`ifdef VERILATOR
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initial begin
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$dumpfile("bram.fst");
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$dumpvars;
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end
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`endif
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endmodule
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@ -0,0 +1,112 @@
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#include <memory>
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#include <cassert>
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#include <limits>
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#include <cstdint>
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#include <cstring>
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#include <cstdlib>
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#include <iostream>
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#include <random>
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#include <unistd.h>
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#include <verilated.h>
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#include "Vbram_interface.h"
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using ModType = Vbram_interface;
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using V = uint32_t;
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ModType *mod;
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constexpr uint32_t start_addr = 0x12340;
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// #define BAILOUT_NUMBER 100000
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#include "../boilerplate.cpp"
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std::array<uint32_t, WORD_AMNT> ram_refresh_data;
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static void handle_ram() {
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static int timer = 0;
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constexpr auto TIMER_MAX = 10;
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bool flip_flop = false;
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if (mod->ram_read) {
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timer++;
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if (timer == TIMER_MAX) {
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mod->ram_valid = 1;
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if (mod->ram_dma_addr < start_addr ||
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mod->ram_dma_addr >= start_addr + WORD_AMNT*4) {
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printf("bad address %x\n", mod->ram_dma_addr);
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exit(1);
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}
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my_assert(mod->ram_dma_addr >= start_addr, "left oob access %x", mod->ram_dma_addr);
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my_assert(mod->ram_dma_addr < start_addr + WORD_AMNT*4, "right oob access %x", mod->ram_dma_addr);
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my_assert(mod->ram_dma_addr % 2 == 0, "unaligned access %x", mod->ram_dma_addr);
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if (mod->ram_dma_addr % 4 == 0) {
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mod->ram_word = ram_refresh_data[(mod->ram_dma_addr - start_addr)/4]& 0xFFFF;
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} else {
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mod->ram_word = ram_refresh_data[(mod->ram_dma_addr - start_addr)/4] >> 16;
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}
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}
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} else {
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mod->ram_valid = 0;
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timer = 0;
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}
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}
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static void handle_read_aa(size_t &i) {
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if (mod->word_ok) {
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uint32_t val = sign_extend(mod->word, 20);
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mod->word_next = 0;
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my_assert(val == ram_refresh_data[i], "received value %x (%zu) != %x", i, val, ram_refresh_data[i]);
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i++;
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} else if (!mod->word_next) {
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mod->word_next = 1;
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}
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}
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/* Test reading the entire array twice. */
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static void test_aa_read_1() {
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size_t ind = 0;
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mod->word_next = 1;
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run_clock();
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while (!mod->word_last || (mod->word_last && mod->word_next)) {
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handle_read_aa(ind);
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run_clock();
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}
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my_assert(ind == WORD_AMNT, "read value %zu != %d\n", ind, WORD_AMNT);
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mod->word_next = 1;
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run_clock();
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ind = 0;
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while (!mod->word_last || (mod->word_last && mod->word_next)) {
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handle_read_aa(ind);
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run_clock();
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}
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my_assert(ind == WORD_AMNT, "second read value %zu != %d\n", ind, WORD_AMNT);
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}
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int main(int argc, char **argv) {
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init(argc, argv);
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for (size_t i = 0; i < RAM_WID; i++) {
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ram_refresh_data[i] = mask_extend(rand(), 20);
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}
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mod->refresh_start = 1;
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mod->start_addr = start_addr;
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run_clock();
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while (!mod->refresh_finished) {
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handle_ram();
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run_clock();
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}
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mod->refresh_start = 0;
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run_clock();
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test_aa_read_1();
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printf("ok\n");
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return 0;
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}
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@ -0,0 +1,76 @@
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#include <cstdio>
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uint32_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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static void _assert(const char *file, int line, const char *exp, bool ev, const char *fmt, ...) {
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if (!ev) {
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va_list va;
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va_start(va, fmt);
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fprintf(stderr, "%s:%d: assertion failed: %s\n", file, line, exp);
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vfprintf(stderr, fmt, va);
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fprintf(stderr, "\n");
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va_end(va);
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exit(1);
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}
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}
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#define STRINGIFY(s) #s
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/* ,##__VA_ARGS__ is a GNU C extension */
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#define my_assert(e, fmt, ...) _assert(__FILE__, __LINE__, STRINGIFY(e), (e), fmt ,##__VA_ARGS__)
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#ifdef BAILOUT_NUMBER
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# define BAILOUT(...) __VA_ARGS__
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#else
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# define BAILOUT(...)
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#endif
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static void run_clock() {
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BAILOUT(static int bailout;)
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for (int i = 0; i < 2; i++) {
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mod->clk = !mod->clk;
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mod->eval();
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main_time++;
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BAILOUT(bailout++;)
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}
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BAILOUT(if (bailout >= BAILOUT_NUMBER) exit(1);)
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}
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#undef BAILOUT
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static void cleanup_exit() {
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mod->final();
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delete mod;
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}
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static void init(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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Verilated::traceEverOn(true);
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mod = new ModType;
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mod->clk = 0;
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atexit(cleanup_exit);
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char *seed = getenv("RANDOM_SEED");
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if (seed) {
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unsigned long i = strtoul(seed, NULL, 10);
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srand((unsigned int)i);
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}
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}
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static V sign_extend(V x, unsigned len) {
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/* if high bit is 1 */
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if (x >> (len - 1) & 1) {
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V mask = (1 << len) - 1;
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return ~mask | x;
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} else {
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return x;
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}
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}
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#define MASK(x,v) ((x) & ((1 << (v)) - 1))
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static V mask_extend(V x, unsigned len) {
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return sign_extend(MASK(x,len), len);
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}
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