From 0a435f6dc8dd72531862273960af4e01e25a1529 Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Sat, 22 Oct 2022 01:58:37 -0400
Subject: [PATCH] rename control loop verilog simulation top level module to
 more descriptive name

---
 firmware/rtl/control_loop/{top.v => control_loop_sim_top.v} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename firmware/rtl/control_loop/{top.v => control_loop_sim_top.v} (100%)

diff --git a/firmware/rtl/control_loop/top.v b/firmware/rtl/control_loop/control_loop_sim_top.v
similarity index 100%
rename from firmware/rtl/control_loop/top.v
rename to firmware/rtl/control_loop/control_loop_sim_top.v