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GUIDELINES: update

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Peter McGoron 2023-03-14 15:59:17 +00:00
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GUIDELINES.md
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@ -10,6 +10,12 @@ See also [Dan Gisselquist][1]'s rules for FPGA development.
synthesizes it incorrectly. synthesizes it incorrectly.
* Do not use parameters that are calculated from other parameters (yosys * Do not use parameters that are calculated from other parameters (yosys
will not parse them correctly). Use macros instead. will not parse them correctly). Use macros instead.
* Only use Verlog macros for basic expression replacement (replacing calculated
parameters). For more advanced code generation, use m4 (see `base.m4` as an
example).
* Add `undefineall` at the end of *every single module*. If you do not,
you will get many confusing errors.
* Do all code and test generation in Makefiles.
* Simulate *every* module, even the trivial ones using Verilator. * Simulate *every* module, even the trivial ones using Verilator.
Simulation must be simulatable with open-source software (Verilator is Simulation must be simulatable with open-source software (Verilator is
preferred, but Icarus Verilog and similar are fine). Put test code in the same preferred, but Icarus Verilog and similar are fine). Put test code in the same