diff --git a/.gitignore b/.gitignore
index 58c0a2c..0e31614 100644
--- a/.gitignore
+++ b/.gitignore
@@ -32,3 +32,5 @@ firmware/rtl/raster/synth.log
 firmware/rtl/raster/synth_test_yosys.v
 firmware/rtl/raster/yosys_output
 firmware/csr_bitwidth.json
+boot/*
+!boot/boot.json
diff --git a/boot/boot.json b/boot/boot.json
new file mode 100644
index 0000000..93d6436
--- /dev/null
+++ b/boot/boot.json
@@ -0,0 +1,6 @@
+{
+	"Image":        "0x40000000",
+	"arty.dtb":     "0x40ef0000",
+	"rootfs.cpio":  "0x41000000",
+	"fw_jump.bin":  "0x40f00000"
+}
diff --git a/doc/maintenance_manual.md b/doc/maintenance_manual.md
index 6e26867..e09418a 100644
--- a/doc/maintenance_manual.md
+++ b/doc/maintenance_manual.md
@@ -169,13 +169,7 @@ TO CONNECT THE FPGA TO THE INTERNET.** The controlling computer can
 still connect to the internet, but through another LAN port. The best
 thing to do is to buy a USB to Ethernet adapter.
 
-You will need some way to do DHCP. The best way is to use a router, but
-a standard wireless router will not fly with any IT department because
-of the security risk. You need to find a non-wireless router (like a
-managed switch). You can even retrofit an old computer into a router
-(just needs another ethernet port).
-
-The default TFTP client connects to 192.168.1.50.
+The default TFTP client connects to 192.168.1.100.
 
 ## Connecting to the FPGA Over USB
 
@@ -194,7 +188,8 @@ better thing to do is to use TFTP boot, which goes over Ethernet.
 CONNECTED NETWORK INTERFACE. THIS IS A BIG SECURITY RISK. ONLY RUN
 TFTP FOR THE AMOUNT OF TIME REQUIRED TO BOOT THE CONTROL SOFTWARE.**
 You can read about how to setup a TFTP server on the [OpenWRT wiki][owrt_wiki].
-On Linux, run
+
+Using DNSMasq on linux, run
 
 	dnsmasq -d --port=0 --enable-tftp --tftp-root=/path/to/firmware/directory --user=root --group=root --interface=$INTERFACE
 
diff --git a/firmware/Makefile b/firmware/Makefile
index 7579741..9550a1a 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -7,7 +7,7 @@ all: rtl_codegen build/digilent_arty/digilent_arty.bit arty.dtb pin_io.c
 rtl_codegen:
 	cd rtl && make
 csr.json build/digilent_arty/digilent_arty.bit: soc.py
-	python3 soc.py
+	TFTP_SERVER_PORT=6969 python3 soc.py
 clean:
 	rm -rf build csr.json overlay.config overlay.dts pin_io.h arty.dts arty.dtb
 	cd rtl && make clean
diff --git a/opensbi/litex/vexriscv/Kconfig b/opensbi/litex/vexriscv/Kconfig
index f81d111..806d366 100644
--- a/opensbi/litex/vexriscv/Kconfig
+++ b/opensbi/litex/vexriscv/Kconfig
@@ -5,5 +5,6 @@ config PLATFORM_LITEX_VEXRISCV
 	select FDT
 	select FDT_SERIAL
 	select TIMER_MTIMER
+	select IPI_MSWI
 	select FDT_SERIAL_LITEX
 	default y
diff --git a/opensbi/litex/vexriscv/objects.mk b/opensbi/litex/vexriscv/objects.mk
index 32f035c..3587e7b 100644
--- a/opensbi/litex/vexriscv/objects.mk
+++ b/opensbi/litex/vexriscv/objects.mk
@@ -1,7 +1,22 @@
 #
 # SPDX-License-Identifier: BSD-2-Clause
 #
+# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
 #
 
+# Command for platform specific "make run"
+platform-runcmd = echo LiteX/VexRiscv
+
+PLATFORM_RISCV_XLEN = 32
+PLATFORM_RISCV_ABI = ilp32
+#PLATFORM_RISCV_ISA = rv32ima ## XXX: Broken on new binutils
+PLATFORM_RISCV_ISA = rv32ima_zicsr_zifencei
+PLATFORM_RISCV_CODE_MODEL = medany
 platform-objs-y += platform.o
+
+# Blobs to build
+FW_TEXT_START=0x40F00000
+FW_JUMP=y
+FW_JUMP_ADDR=0x40000000
+FW_JUMP_FDT_ADDR=0x40EF0000