refactor soc.py base.v interface
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parent
69f16264dd
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11f7cfd388
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@ -19,6 +19,7 @@ m4_define(m4_dac_wires, ⟨
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input wf_refresh_start_$2,
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input [WF_RAM_WID-1:0] wf_start_addr_$2,
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output wf_refresh_finished_$2,
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output wf_running_$2,
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output [WF_RAM_WID-1:0] wf_ram_dma_addr_$2,
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input [WF_RAM_WORD_WID-1:0] wf_ram_word_$2,
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@ -94,6 +95,7 @@ m4_define(m4_dac_switch, ⟨
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.clk(clk),
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.arm(wf_arm_$2),
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.halt_on_finish(wf_halt_on_finish_$2),
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.running(wf_running_$2),
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.finished(wf_finished_$2),
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.time_to_wait(wf_time_to_wait_$2),
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.refresh_start(wf_refresh_start_$2),
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253
firmware/soc.py
253
firmware/soc.py
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@ -32,238 +32,87 @@ io = [
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class Base(Module, AutoCSR):
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def __init__(self, clk, sdram, platform):
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kwargs = {}
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for i in range(0,8):
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setattr(self, f"dac_sel_{i}", CSRStorage(3, name=f"dac_sel_{i}"))
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kwargs[f"dac_sel_{i}"] = getattr(self, f"dac_sel_{i}")
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setattr(self, f"dac_finished_{i}", CSRStatus(1, name=f"dac_finished_{i}"))
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kwargs[f"dac_finished_{i}"] = getattr(finishedf, f"dac_finished_{i}")
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setattr(self, f"dac_arm_{i}", CSRStorage(1, name=f"dac_arm_{i}"))
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kwargs[f"dac_arm_{i}"] = getattr(armf, f"dac_arm_{i}")
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setattr(self, f"from_dac_{i}", CSRStatus(24, name=f"from_dac_{i}"))
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kwargs[f"from_dac_{i}"] = getattr(armf, f"from_dac_{i}")
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setattr(self, f"to_dac_{i}", CSRStorage(24, name=f"to_dac_{i}"))
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kwargs[f"to_dac_{i}"] = getattr(armf, f"to_dac_{i}")
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setattr(self, f"wf_arm_{i}", CSRStorage(1, name=f"wf_arm_{i}"))
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kwargs[f"wf_arm_{i}"] = getattr(armf, f"wf_arm_{i}")
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setattr(self, f"wf_halt_on_finish_{i}", CSRStorage(1, name=f"wf_halt_on_finish_{i}")),
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kwargs[f"wf_halt_on_finish_{i}"] = getattr(armf, f"wf_halt_on_finish_{i}")
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setattr(self, f"wf_finished_{i}", CSRStatus(1, name=f"wf_finished_{i}")),
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kwargs[f"wf_finished_{i}"] = getattr(armf, f"wf_finished_{i}")
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setattr(self, f"wf_running_{i}", CSRStatus(1, name=f"wf_running_{i}")),
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kwargs[f"wf_running_{i}"] = getattr(armf, f"wf_running_{i}")
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setattr(self, f"wf_time_to_wait_{i}", CSRStorage(16, name=f"wf_time_to_wait_{i}"))
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kwargs[f"wf_time_to_wait_{i}"] = getattr(armf, f"wf_time_to_wait_{i}")
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setattr(self, f"wf_refresh_start_{i}", CSRStorage(1, name=f"wf_refresh_start_{i}"))
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kwargs[f"wf_refresh_start_{i}"] = getattr(armf, f"wf_refresh_start_{i}")
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setattr(self, f"wf_refresh_finished_{i}", CSRStatus(1, name=f"wf_refresh_finished_{i}"))
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kwargs[f"wf_refresh_finished_{i}"] = getattr(armf, f"wf_refresh_finished_{i}")
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setattr(self, f"wf_start_addr_{i}", CSRStorage(32, name=f"wf_start_addr_{i}"))
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kwargs[f"wf_start_addr_{i}"] = getattr(armf, f"wf_start_addr_{i}")
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port = sdram.crossbar.get_port()
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setattr(self, f"wf_sdram_{i}", LiteDRAMDMAReader(port))
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kwargs[f"wf_sdram_{i}"] = getattr(armf, f"wf_sdram_{i}")
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setattr(self, f"adc_finished_{i}", CSRStatus(1, name=f"adc_finished_{i}"))
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kwargs[f"adc_finished_{i}"] = getattr(armf, f"adc_finished_{i}")
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setattr(self, f"adc_arm_{i}", CSRStorage(1, name=f"adc_arm_{i}"))
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kwargs[f"adc_arm_{i}"] = getattr(armf, f"adc_arm_{i}")
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setattr(self, f"from_adc_{i}", CSRStatus(32, name=f"from_adc_{i}"))
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kwargs[f"from_adc_{i}"] = getattr(armf, f"from_adc_{i}")
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self.adc_sel_0 = CSRStorage(2)
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kwargs["adc_sel_0"] = self.adc_sel_0
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self.cl_in_loop = CSRStatus(1)
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kwargs["o_cl_in_loop"] = self.cl_in_loop.status
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self.cl_cmd = CSRStorage(64)
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kwargs["i_cl_cmd"] = self.cl_cmd.storage
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self.cl_word_in = CSRStorage(32)
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kwargs["i_cl_word_in"] = self.cl_word_in.storage
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self.cl_word_out = CSRStatus(32)
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kwargs["o_cl_word_out"] = self.cl_word_out.status
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self.cl_start_cmd = CSRStorage(1)
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kwargs["i_cl_start_cmd"] = self.cl_start_cmd.storage
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self.cl_finish_cmd = CSRStatus(1)
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kwargs["o_cl_finish_cmd"] = self.cl_finish_cmd.status
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self.specials += Instance("base",
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i_clk = clk,
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i_dac_miso = platform.request("dac_miso"),
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o_dac_mosi = platform.request("dac_mosi"),
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o_dac_sck = platform.request("dac_sck"),
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o_dac_ss_L = platform.request("dac_ss_L"),
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o_adc_conv = platform.request("adc_conv"),
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i_adc_sdo = platform.request("adc_sdo"),
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o_adc_sck = platform.request("adc_sck"),
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kwargs["i_clk"] = clk
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kwargs["i_dac_miso"] = platform.request("dac_miso")
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kwargs["o_dac_mosi"] = platform.request("dac_mosi")
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kwargs["o_dac_sck"] = platform.request("dac_sck")
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kwargs["o_dac_ss_L"] = platform.request("dac_ss_L")
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kwargs["o_adc_conv"] = platform.request("adc_conv")
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kwargs["i_adc_sdo"] = platform.request("adc_sdo")
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kwargs["o_adc_sck"] = platform.request("adc_sck")
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# dac_0
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i_dac_sel_0 = self.dac_sel_0.storage,
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o_dac_finished_0 = self.dac_finished_0.status,
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i_dac_arm_0 = self.dac_arm_0.storage,
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o_from_dac_0 = self.from_dac_0.status,
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i_to_dac_0 = self.to_dac_0.storage,
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i_wf_arm_0 = self.wf_arm_0.storage,
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i_wf_time_to_wait_0 = self.wf_time_to_wait_0.storage,
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i_wf_refresh_start_0 = self.wf_refresh_start_0.storage,
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o_wf_refresh_finished_0 = self.wf_refresh_finished_0.status,
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o_wf_start_addr_0 = self.wf_start_addr_0.storage,
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o_wf_ram_dma_addr_0 = self.wf_sdram_0.sink.address,
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i_wf_ram_word_0 = self.wf_sdram_0.source.data,
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o_wf_ram_read_0 = self.wf_sdram_0.sink.valid,
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i_wf_ram_valid_0 = self.wf_sdram_0.source.valid,
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# dac_1
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i_dac_sel_1 = self.dac_sel_1.storage,
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o_dac_finished_1 = self.dac_finished_1.status,
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i_dac_arm_1 = self.dac_arm_1.storage,
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o_from_dac_1 = self.from_dac_1.status,
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i_to_dac_1 = self.to_dac_1.storage,
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i_wf_arm_1 = self.wf_arm_1.storage,
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i_wf_time_to_wait_1 = self.wf_time_to_wait_1.storage,
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i_wf_refresh_start_1 = self.wf_refresh_start_1.storage,
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o_wf_refresh_finished_1 = self.wf_refresh_finished_1.status,
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o_wf_start_addr_1 = self.wf_start_addr_1.storage,
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o_wf_ram_dma_addr_1 = self.wf_sdram_1.sink.address,
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i_wf_ram_word_1 = self.wf_sdram_1.source.data,
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o_wf_ram_read_1 = self.wf_sdram_1.sink.valid,
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i_wf_ram_valid_1 = self.wf_sdram_1.source.valid,
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# dac_2
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i_dac_sel_2 = self.dac_sel_2.storage,
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o_dac_finished_2 = self.dac_finished_2.status,
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i_dac_arm_2 = self.dac_arm_2.storage,
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o_from_dac_2 = self.from_dac_2.status,
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i_to_dac_2 = self.to_dac_2.storage,
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i_wf_arm_2 = self.wf_arm_2.storage,
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i_wf_time_to_wait_2 = self.wf_time_to_wait_2.storage,
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i_wf_refresh_start_2 = self.wf_refresh_start_2.storage,
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o_wf_refresh_finished_2 = self.wf_refresh_finished_2.status,
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o_wf_start_addr_2 = self.wf_start_addr_2.storage,
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o_wf_ram_dma_addr_2 = self.wf_sdram_2.sink.address,
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i_wf_ram_word_2 = self.wf_sdram_2.source.data,
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o_wf_ram_read_2 = self.wf_sdram_2.sink.valid,
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i_wf_ram_valid_2 = self.wf_sdram_2.source.valid,
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# dac_3
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i_dac_sel_3 = self.dac_sel_3.storage,
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o_dac_finished_3 = self.dac_finished_3.status,
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i_dac_arm_3 = self.dac_arm_3.storage,
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o_from_dac_3 = self.from_dac_3.status,
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i_to_dac_3 = self.to_dac_3.storage,
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i_wf_arm_3 = self.wf_arm_3.storage,
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i_wf_time_to_wait_3 = self.wf_time_to_wait_3.storage,
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i_wf_refresh_start_3 = self.wf_refresh_start_3.storage,
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o_wf_refresh_finished_3 = self.wf_refresh_finished_3.status,
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o_wf_start_addr_3 = self.wf_start_addr_3.storage,
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o_wf_ram_dma_addr_3 = self.wf_sdram_3.sink.address,
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i_wf_ram_word_3 = self.wf_sdram_3.source.data,
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o_wf_ram_read_3 = self.wf_sdram_3.sink.valid,
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i_wf_ram_valid_3 = self.wf_sdram_3.source.valid,
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# dac_4
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i_dac_sel_4 = self.dac_sel_4.storage,
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o_dac_finished_4 = self.dac_finished_4.status,
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i_dac_arm_4 = self.dac_arm_4.storage,
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o_from_dac_4 = self.from_dac_4.status,
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i_to_dac_4 = self.to_dac_4.storage,
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i_wf_arm_4 = self.wf_arm_4.storage,
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i_wf_time_to_wait_4 = self.wf_time_to_wait_4.storage,
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i_wf_refresh_start_4 = self.wf_refresh_start_4.storage,
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o_wf_refresh_finished_4 = self.wf_refresh_finished_4.status,
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o_wf_start_addr_4 = self.wf_start_addr_4.storage,
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o_wf_ram_dma_addr_4 = self.wf_sdram_4.sink.address,
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i_wf_ram_word_4 = self.wf_sdram_4.source.data,
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o_wf_ram_read_4 = self.wf_sdram_4.sink.valid,
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i_wf_ram_valid_4 = self.wf_sdram_4.source.valid,
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# dac_5
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i_dac_sel_5 = self.dac_sel_5.storage,
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o_dac_finished_5 = self.dac_finished_5.status,
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i_dac_arm_5 = self.dac_arm_5.storage,
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o_from_dac_5 = self.from_dac_5.status,
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i_to_dac_5 = self.to_dac_5.storage,
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i_wf_arm_5 = self.wf_arm_5.storage,
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i_wf_time_to_wait_5 = self.wf_time_to_wait_5.storage,
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i_wf_refresh_start_5 = self.wf_refresh_start_5.storage,
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o_wf_refresh_finished_5 = self.wf_refresh_finished_5.status,
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o_wf_start_addr_5 = self.wf_start_addr_5.storage,
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o_wf_ram_dma_addr_5 = self.wf_sdram_5.sink.address,
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i_wf_ram_word_5 = self.wf_sdram_5.source.data,
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o_wf_ram_read_5 = self.wf_sdram_5.sink.valid,
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i_wf_ram_valid_5 = self.wf_sdram_5.source.valid,
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# dac_6
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i_dac_sel_6 = self.dac_sel_6.storage,
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o_dac_finished_6 = self.dac_finished_6.status,
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i_dac_arm_6 = self.dac_arm_6.storage,
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o_from_dac_6 = self.from_dac_6.status,
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i_to_dac_6 = self.to_dac_6.storage,
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i_wf_arm_6 = self.wf_arm_6.storage,
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i_wf_time_to_wait_6 = self.wf_time_to_wait_6.storage,
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i_wf_refresh_start_6 = self.wf_refresh_start_6.storage,
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o_wf_refresh_finished_6 = self.wf_refresh_finished_6.status,
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o_wf_start_addr_6 = self.wf_start_addr_6.storage,
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o_wf_ram_dma_addr_6 = self.wf_sdram_6.sink.address,
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i_wf_ram_word_6 = self.wf_sdram_6.source.data,
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o_wf_ram_read_6 = self.wf_sdram_6.sink.valid,
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i_wf_ram_valid_6 = self.wf_sdram_6.source.valid,
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# dac_7
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i_dac_sel_7 = self.dac_sel_7.storage,
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o_dac_finished_7 = self.dac_finished_7.status,
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i_dac_arm_7 = self.dac_arm_7.storage,
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o_from_dac_7 = self.from_dac_7.status,
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i_to_dac_7 = self.to_dac_7.storage,
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i_wf_arm_7 = self.wf_arm_7.storage,
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i_wf_time_to_wait_7 = self.wf_time_to_wait_7.storage,
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i_wf_refresh_start_7 = self.wf_refresh_start_7.storage,
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o_wf_refresh_finished_7 = self.wf_refresh_finished_7.status,
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o_wf_start_addr_7 = self.wf_start_addr_7.storage,
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o_wf_ram_dma_addr_7 = self.wf_sdram_7.sink.address,
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i_wf_ram_word_7 = self.wf_sdram_7.source.data,
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o_wf_ram_read_7 = self.wf_sdram_7.sink.valid,
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i_wf_ram_valid_7 = self.wf_sdram_7.source.valid,
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i_adc_sel_0 = self.adc_sel_0.storage,
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# adc_0
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o_adc_finished_0 = self.adc_finished_0.status,
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i_adc_arm_0 = self.adc_arm_0.storage,
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o_from_adc_0 = self.from_adc_0.status,
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# adc_1
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o_adc_finished_1 = self.adc_finished_1.status,
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i_adc_arm_1 = self.adc_arm_1.storage,
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o_from_adc_1 = self.from_adc_1.status,
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# adc_2
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o_adc_finished_2 = self.adc_finished_2.status,
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i_adc_arm_2 = self.adc_arm_2.storage,
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o_from_adc_2 = self.from_adc_2.status,
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# adc_3
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o_adc_finished_3 = self.adc_finished_3.status,
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i_adc_arm_3 = self.adc_arm_3.storage,
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o_from_adc_3 = self.from_adc_3.status,
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# adc_4
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o_adc_finished_4 = self.adc_finished_4.status,
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i_adc_arm_4 = self.adc_arm_4.storage,
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o_from_adc_4 = self.from_adc_4.status,
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# adc_5
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o_adc_finished_5 = self.adc_finished_5.status,
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i_adc_arm_5 = self.adc_arm_5.storage,
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o_from_adc_5 = self.from_adc_5.status,
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# adc_6
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o_adc_finished_6 = self.adc_finished_6.status,
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i_adc_arm_6 = self.adc_arm_6.storage,
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o_from_adc_6 = self.from_adc_6.status,
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# adc_7
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o_adc_finished_7 = self.adc_finished_7.status,
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i_adc_arm_7 = self.adc_arm_7.storage,
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o_from_adc_7 = self.from_adc_7.status,
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o_cl_in_loop = self.cl_in_loop.status,
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i_cl_cmd = self.cl_cmd.storage,
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i_cl_word_in = self.cl_word_in.storage,
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o_cl_word_out = self.cl_word_out.status,
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i_cl_start_cmd = self.cl_start_cmd.storage,
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o_cl_finish_cmd = self.cl_finish_cmd.status
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)
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self.specials += Instance("base", **kwargs)
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# Clock and Reset Generator
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class _CRG(Module):
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