ram_fifo: add empty and full ports

firmware/rtl/raster/ram_fifo.v

@@ -1,7 +1,7 @@
 module ram_fifo #(
 	parameter DAT_WID = 24,
-	parameter FIFO_DEPTH = 1500,
-	parameter FIFO_DEPTH_WID = 11
+	parameter FIFO_DEPTH_WID = 11,
+	parameter [FIFO_DEPTH_WID-1:0] FIFO_DEPTH = 1500
 ) (
 	input clk,
 	input rst,
@@ -10,10 +10,16 @@ module ram_fifo #(
 	input write_enable,
 
 	input signed [DAT_WID-1:0] write_dat,
-	output reg [FIFO_DEPTH_WID-1:0] fifo_size,
-	output signed [DAT_WID-1:0] read_dat
+	output signed [DAT_WID-1:0] read_dat,
+	output empty,
+	output full
 );
 
+reg [FIFO_DEPTH_WID-1:0] fifo_size;
+initial fifo_size = 0;
+assign empty = fifo_size == 0;
+assign full = fifo_size == FIFO_DEPTH;
+
 ram_fifo_dual_port #(
 	.DAT_WID(DAT_WID),
 	.FIFO_DEPTH(FIFO_DEPTH),
@@ -48,4 +54,13 @@ always @ (posedge clk) begin
 	end
 end
 
+/*
+`ifdef VERILATOR
+initial begin
+	$dumpfile("ram_fifo.vcd");
+	$dumpvars;
+end
+`endif
+*/
+
 endmodule

firmware/rtl/raster/ram_fifo_dual_port.v

@@ -34,6 +34,9 @@ always @ (posedge RCLK) begin
 		read_ptr <= 0;
 	end else if (read_enable) begin
 		read_dat <= memory[read_ptr];
+		if (read_ptr == FIFO_DEPTH-1)
+			read_ptr <= 0;
+		else
 			read_ptr <= read_ptr + 1;
 	end
 end
@@ -45,6 +48,9 @@ always @ (posedge WCLK) begin
 		write_ptr <= 0;
 	end else if (write_enable) begin
 		memory[write_ptr] <= write_dat;
+		if (write_ptr == FIFO_DEPTH-1)
+			write_ptr <= 0;
+		else
 			write_ptr <= write_ptr + 1;
 	end
 end

firmware/rtl/raster/ram_fifo_sim.cpp

@@ -1,4 +1,5 @@
 #include <memory>
+#include <cassert>
 #include <limits>
 #include <cstdint>
 #include <cstring>
@@ -6,7 +7,6 @@
 #include <iostream>
 #include <random>
 #include <unistd.h>
-
 #include <verilated.h>
 #include "Vram_fifo.h"
 using ModType = Vram_fifo;
@@ -14,6 +14,10 @@ ModType *mod;
 
 uint32_t main_time = 0;
 
+double sc_time_stamp() {
+	return main_time;
+}
+
 static void run_clock() {
 	for (int i = 0; i < 2; i++) {
 		mod->clk = !mod->clk;
@@ -42,10 +46,11 @@ static void init_values() {
 	mod->write_dat = 0;
 }
 
-#define MAX_VALS 32000/24
+#define MAX_VALS 1500
 uint32_t vals[MAX_VALS];
 
 static void push(uint32_t v) {
+	assert(!mod->full);
 	mod->write_dat = v;
 	mod->write_enable = 1;
 	run_clock();
@@ -54,30 +59,47 @@ static void push(uint32_t v) {
 }
 
 static void pop(int i) {
+	assert(!mod->empty);
 	mod->read_enable = 1;
 	run_clock();
 	mod->read_enable = 0;
 	run_clock();
 }
 
+static void push_random(int start, int end) {
+	for (int i = start; i < end; i++) {
+		vals[i] = rand() & 0xFFFFFFFFFFFF;
+		printf("%d\n", i);
+		push(vals[i]);
+	}
+}
+
+static void pop_random(int start, int end) {
+	for (int i = start; i < end; i++) {
+		pop(i);
+		if (mod->read_dat != vals[i]) {
+			fprintf(stderr, "expect %u, %u\n", vals[i], mod->read_dat);
+			exit(1);
+		}
+	}
+}
+
 int main(int argc, char **argv) {
 	init(argc, argv);
 	init_values();
 	run_clock();
+	assert(mod->empty);
 
-	/* Simple test */
-	for (int i = 0; i < MAX_VALS; i++) {
-		vals[i] = rand() & 0xFFFFFFFFFFFF;
-		push(vals[i]);
-	}
+	push_random(0, MAX_VALS);
+	assert(mod->full);
 
-	for (int i = 0; i < MAX_VALS; i++) {
-		pop(i);
-		if (mod->read_dat != vals[i]) {
-			fprintf(stderr, "expect %u, %u\n", vals[i], mod->read_dat);
-			return 1;
-		}
-	}
+	pop_random(0, MAX_VALS);
+	assert(mod->empty);
+
+	push_random(0, 50);
+	pop_random(0, 20);
+	push_random(50, 100);
+	pop_random(20, 100);
 
 	return 0;
 }