From 24f66c1a701434f05ba4ecb9c53ac39318e66f02 Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Tue, 30 May 2023 17:32:04 -0400
Subject: [PATCH] firmware/soc.py: switch to VexRiscV-SMP (with one core) to
 make litex happy

---
 firmware/soc.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/firmware/soc.py b/firmware/soc.py
index 78d2e61..d4b2a5b 100644
--- a/firmware/soc.py
+++ b/firmware/soc.py
@@ -259,7 +259,9 @@ class UpsilonSoC(SoCCore):
 				bus_data_width = 32,
 				bus_address_width = 32,
 				bus_timeout = int(1e6),
-				cpu_type = "vexriscv",
+				cpu_type = "vexriscv_smp",
+                cpu_count = 1,
+                cpu_variant="linux",
 				integrated_rom_size=0x20000,
 				integrated_sram_size = 0x2000,
 				csr_data_width=32,