diff --git a/build/Dockerfile.buildroot b/build/Dockerfile.buildroot index 7f98825..c6f78a0 100644 --- a/build/Dockerfile.buildroot +++ b/build/Dockerfile.buildroot @@ -1,18 +1,8 @@ -# Copyright 2023 Peter McGoron -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 +# Copyright 2023 (C) Peter McGoron +# +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. FROM debian:bookworm diff --git a/build/Dockerfile.litex_f4pga b/build/Dockerfile.litex_f4pga index 3688e2d..b960804 100644 --- a/build/Dockerfile.litex_f4pga +++ b/build/Dockerfile.litex_f4pga @@ -1,18 +1,8 @@ -# Copyright 2023 Peter McGoron +# Copyright 2023 (C) Peter McGoron # -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. FROM debian:bookworm diff --git a/build/Dockerfile.opensbi b/build/Dockerfile.opensbi index f67e962..4f8a12b 100644 --- a/build/Dockerfile.opensbi +++ b/build/Dockerfile.opensbi @@ -1,18 +1,8 @@ -# Copyright 2023 Peter McGoron +# Copyright 2023 (C) Peter McGoron # -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. FROM debian:bookworm diff --git a/build/Dockerfile.verilator b/build/Dockerfile.verilator index 3d0fe97..16b28f0 100644 --- a/build/Dockerfile.verilator +++ b/build/Dockerfile.verilator @@ -1,18 +1,8 @@ -# Copyright 2023 Peter McGoron +# Copyright 2023 (C) Peter McGoron # -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. FROM debian:bookworm diff --git a/build/Makefile b/build/Makefile index 968363b..41a2121 100644 --- a/build/Makefile +++ b/build/Makefile @@ -1,6 +1,8 @@ -# Copyright 2023 Peter McGoron -# -# SPDX-License-Identifier: Apache-2.0 +# Copyright 2023 (C) Peter McGoron +# +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. .PHONY: images f4pga buildroot litex clone help attach hardware-image \ buildroot-image litex-f4pga-image \ @@ -112,7 +114,7 @@ buildroot-clean: ###### TFTP tftp: - cd upsilon/boot && py3tftp --host 192.168.1.100 -p 6969 -v + cd ../boot && py3tftp --host 192.168.1.100 -p 6969 -v ###### External projects @@ -142,9 +144,9 @@ litex: git checkout -B upsilon_stable c6ccb626e88168045edacced3743f6bd98746742 upsilon-hardware.tar.gz: - tar -czvf upsilon-hardware.tar.gz ../gateware/ + tar -czvf upsilon-hardware.tar.gz ../gateware/ --transform 's|gateware|upsilon/gateware|' upsilon-buildroot.tar.gz: - tar -czvf upsilon-buildroot.tar.gz ../buildroot/ + tar -czvf upsilon-buildroot.tar.gz ../buildroot/ --transform 's|buildroot|upsilon/buildroot|' # This script only works for GNU tar. It renames the extraction directory. upsilon-opensbi.tar.gz: tar -czvf upsilon-opensbi.tar.gz ../opensbi/ --transform 's|opensbi|opensbi/platform|' diff --git a/buildroot/board/litex_vexriscv/linux.config b/buildroot/board/litex_vexriscv/linux.config index 9c3dc11..718b26f 100644 --- a/buildroot/board/litex_vexriscv/linux.config +++ b/buildroot/board/litex_vexriscv/linux.config @@ -1,3 +1,9 @@ +# Copyright 2023 (C) Peter McGoron +# +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. + CONFIG_SECTION_MISMATCH_WARN_ONLY=y # Architecture diff --git a/buildroot/configs/litex_vexriscv_defconfig b/buildroot/configs/litex_vexriscv_defconfig index 4ba37c7..1c01c0b 100644 --- a/buildroot/configs/litex_vexriscv_defconfig +++ b/buildroot/configs/litex_vexriscv_defconfig @@ -1,3 +1,8 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. +# #Target options BR2_riscv=y BR2_RISCV_32=y diff --git a/doc/copying/README.md b/doc/copying/README.md index 2463256..744c223 100644 --- a/doc/copying/README.md +++ b/doc/copying/README.md @@ -1,5 +1,12 @@ -Upsilon is a copyleft hardware project, which brings its own difficulties. -Upsilon is dual-licensed in many locations. +Copyright (C) Peter McGoron + +This file is a part of Upsilon, a free and open source software project. +For license terms, refer to the files in `doc/copying` in the Upsilon +source distribution. + +__________________________________________________________________________ + +Upsilon is governed by multiple open-source licenses. The files under `gateware/` are disjunctive dual-licensed under the CERN-OHL-S v2.0 (or any later version), or the GNU GPL v3.0 (or any later version). @@ -23,3 +30,16 @@ Any other file is licensed under the GNU GPL v3.0 (or any later version). Some files contain additional licenses. You must comply with the terms of both the license in a file and the licenses specified here. + +## Guidelines + +Each file should have the following header in a comment: + + Copyright year (C) John Doe + Copyright year (C) Jane Doe + ... + This file is a part of Upsilon, a free and open source software project. + For license terms, refer to the files in `doc/copying` in the Upsilon + source distribution. + +Add your name to files that you have added a notable amount to. diff --git a/gateware/Makefile b/gateware/Makefile index fba4245..255a297 100644 --- a/gateware/Makefile +++ b/gateware/Makefile @@ -1,3 +1,9 @@ +# Copyright 2023 (C) Peter McGoron +# +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. +# .PHONY: cpu clean rtl_codegen DEVICETREE_GEN_DIR=. diff --git a/gateware/rtl/Makefile b/gateware/rtl/Makefile index a88a6c8..027ec6c 100644 --- a/gateware/rtl/Makefile +++ b/gateware/rtl/Makefile @@ -1,3 +1,8 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. + all: make_base make_spi make_control_loop test: diff --git a/gateware/rtl/base/base.v.m4 b/gateware/rtl/base/base.v.m4 index 0772fb3..dcfdc80 100644 --- a/gateware/rtl/base/base.v.m4 +++ b/gateware/rtl/base/base.v.m4 @@ -2,6 +2,13 @@ m4_changequote(`⟨', `⟩') m4_changecom(⟨/*⟩, ⟨*/⟩) m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩) m4_include(../control_loop/control_loop_cmds.m4) +/* +# Copyright 2023 (C) Peter McGoron +# +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. +*/ /* Since yosys only allows for standard Verilog (no system verilog), * arrays (which would make everything much cleaner) cannot be used. diff --git a/gateware/rtl/common.makefile b/gateware/rtl/common.makefile index 4d9df90..988eaf4 100644 --- a/gateware/rtl/common.makefile +++ b/gateware/rtl/common.makefile @@ -1,3 +1,8 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. + # Generate verilog from m4 file #m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@ # NOTE: f4pga yosys does not support `line directives. Use above for debug. diff --git a/gateware/rtl/control_loop/Makefile b/gateware/rtl/control_loop/Makefile index ab9694b..8fa27c6 100644 --- a/gateware/rtl/control_loop/Makefile +++ b/gateware/rtl/control_loop/Makefile @@ -1,3 +1,8 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. + # Makefile for tests and hardware verification. .PHONY: test clean codegen all diff --git a/gateware/rtl/control_loop/adc_sim.v b/gateware/rtl/control_loop/adc_sim.v index 5647e9a..b3ed167 100644 --- a/gateware/rtl/control_loop/adc_sim.v +++ b/gateware/rtl/control_loop/adc_sim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ module adc_sim #( parameter POLARITY = 1, parameter PHASE = 0, diff --git a/gateware/rtl/control_loop/boothmul.v b/gateware/rtl/control_loop/boothmul.v index 5583004..c6a99b7 100644 --- a/gateware/rtl/control_loop/boothmul.v +++ b/gateware/rtl/control_loop/boothmul.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Booth Multiplication v1.1 * Written by Peter McGoron, 2022. * diff --git a/gateware/rtl/control_loop/boothmul_sim.cpp b/gateware/rtl/control_loop/boothmul_sim.cpp index 7edf0bf..a02d1ce 100644 --- a/gateware/rtl/control_loop/boothmul_sim.cpp +++ b/gateware/rtl/control_loop/boothmul_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/control_loop/control_loop.v.m4 b/gateware/rtl/control_loop/control_loop.v.m4 index d9db131..a5c2656 100644 --- a/gateware/rtl/control_loop/control_loop.v.m4 +++ b/gateware/rtl/control_loop/control_loop.v.m4 @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ m4_changequote(`⟨', `⟩') m4_changecom(⟨/*⟩, ⟨*/⟩) m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩) diff --git a/gateware/rtl/control_loop/control_loop_cmds.h.m4 b/gateware/rtl/control_loop/control_loop_cmds.h.m4 index cd436a9..dd8ec90 100644 --- a/gateware/rtl/control_loop/control_loop_cmds.h.m4 +++ b/gateware/rtl/control_loop/control_loop_cmds.h.m4 @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ m4_changequote(`⟨', `⟩')m4_dnl m4_changecom(⟨/*⟩, ⟨*/⟩)m4_dnl m4_define(generate_macro, ⟨m4_dnl diff --git a/gateware/rtl/control_loop/control_loop_cmds.m4 b/gateware/rtl/control_loop/control_loop_cmds.m4 index c561bee..e849546 100644 --- a/gateware/rtl/control_loop/control_loop_cmds.m4 +++ b/gateware/rtl/control_loop/control_loop_cmds.m4 @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ generate_macro(CONTROL_LOOP_NOOP, 0) generate_macro(CONTROL_LOOP_STATUS, 1) generate_macro(CONTROL_LOOP_SETPT, 2) diff --git a/gateware/rtl/control_loop/control_loop_cmds.vh.m4 b/gateware/rtl/control_loop/control_loop_cmds.vh.m4 index fae1a66..5d5ff44 100644 --- a/gateware/rtl/control_loop/control_loop_cmds.vh.m4 +++ b/gateware/rtl/control_loop/control_loop_cmds.vh.m4 @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ m4_changequote(`⟨', `⟩')m4_dnl m4_changecom(⟨/*⟩, ⟨*/⟩)m4_dnl m4_define(generate_macro, ⟨m4_dnl diff --git a/gateware/rtl/control_loop/control_loop_math.v.m4 b/gateware/rtl/control_loop/control_loop_math.v.m4 index 9301f0a..fdef35b 100644 --- a/gateware/rtl/control_loop/control_loop_math.v.m4 +++ b/gateware/rtl/control_loop/control_loop_math.v.m4 @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ m4_changequote(`⟨', `⟩') m4_changecom(⟨/*⟩, ⟨*/⟩) /*************** Precision ************** diff --git a/gateware/rtl/control_loop/control_loop_math_implementation.cpp b/gateware/rtl/control_loop/control_loop_math_implementation.cpp index 3459da7..7d45252 100644 --- a/gateware/rtl/control_loop/control_loop_math_implementation.cpp +++ b/gateware/rtl/control_loop/control_loop_math_implementation.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include "control_loop_math_implementation.h" #define BITMASK(n) (((V)1 << (n)) - 1) diff --git a/gateware/rtl/control_loop/control_loop_math_implementation.h b/gateware/rtl/control_loop/control_loop_math_implementation.h index 8a8eda9..88ebc2c 100644 --- a/gateware/rtl/control_loop/control_loop_math_implementation.h +++ b/gateware/rtl/control_loop/control_loop_math_implementation.h @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #pragma once #include #include diff --git a/gateware/rtl/control_loop/control_loop_math_sim.cpp b/gateware/rtl/control_loop/control_loop_math_sim.cpp index 6543ed3..d39b1e7 100644 --- a/gateware/rtl/control_loop/control_loop_math_sim.cpp +++ b/gateware/rtl/control_loop/control_loop_math_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* TODO: add ADC_TO_DAC multiplication and verify */ #include #include diff --git a/gateware/rtl/control_loop/control_loop_sim.cpp b/gateware/rtl/control_loop/control_loop_sim.cpp index fe262ca..8b1c0e0 100644 --- a/gateware/rtl/control_loop/control_loop_sim.cpp +++ b/gateware/rtl/control_loop/control_loop_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/control_loop/control_loop_sim_interactive.cpp b/gateware/rtl/control_loop/control_loop_sim_interactive.cpp index 55d415a..e4e0f2d 100644 --- a/gateware/rtl/control_loop/control_loop_sim_interactive.cpp +++ b/gateware/rtl/control_loop/control_loop_sim_interactive.cpp @@ -1,3 +1,9 @@ +/* Copyright 2022 (C) Peter McGoron + * Copyright 2022 (C) Nicolas Azzi + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/control_loop/control_loop_sim_top.v b/gateware/rtl/control_loop/control_loop_sim_top.v index 2df0c98..49bbf17 100644 --- a/gateware/rtl/control_loop/control_loop_sim_top.v +++ b/gateware/rtl/control_loop/control_loop_sim_top.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `include "control_loop_cmds.vh" module control_loop_sim_top #( diff --git a/gateware/rtl/control_loop/dac_sim.v b/gateware/rtl/control_loop/dac_sim.v index 55f9140..9400a0b 100644 --- a/gateware/rtl/control_loop/dac_sim.v +++ b/gateware/rtl/control_loop/dac_sim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ module dac_sim #( parameter POLARITY = 0, parameter PHASE = 1, diff --git a/gateware/rtl/control_loop/intsat.v b/gateware/rtl/control_loop/intsat.v index 41f1d12..1cf9c73 100644 --- a/gateware/rtl/control_loop/intsat.v +++ b/gateware/rtl/control_loop/intsat.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Saturate integers. v0.1 * Written by Peter McGoron, 2022. */ diff --git a/gateware/rtl/control_loop/intsat_sim.cpp b/gateware/rtl/control_loop/intsat_sim.cpp index c391085..c35de4e 100644 --- a/gateware/rtl/control_loop/intsat_sim.cpp +++ b/gateware/rtl/control_loop/intsat_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/control_loop/intsat_testbench.v b/gateware/rtl/control_loop/intsat_testbench.v index 2b4660d..c716598 100644 --- a/gateware/rtl/control_loop/intsat_testbench.v +++ b/gateware/rtl/control_loop/intsat_testbench.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ //testbench for intsat module //Timothy Burman, 2022 diff --git a/gateware/rtl/control_loop/sign_extend.v b/gateware/rtl/control_loop/sign_extend.v index ec0b8fd..08bd3b6 100644 --- a/gateware/rtl/control_loop/sign_extend.v +++ b/gateware/rtl/control_loop/sign_extend.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ module sign_extend #( parameter WID1 = 18, parameter WID2 = 24 diff --git a/gateware/rtl/control_loop/yosys_test.sh b/gateware/rtl/control_loop/yosys_test.sh deleted file mode 100644 index a983d3c..0000000 --- a/gateware/rtl/control_loop/yosys_test.sh +++ /dev/null @@ -1 +0,0 @@ -yosys -p "plugin -i systemverilog" -p "read_systemverilog control_loop.v control_loop_math.v ../spi/spi_master_ss_no_write.v ../spi/spi_master_ss.v boothmul.v intsat.v ../spi/spi_master.v ../spi/spi_master_no_write.v" -p "synth_xilinx" diff --git a/gateware/rtl/raster/Makefile b/gateware/rtl/raster/Makefile index 445f914..718e7f5 100644 --- a/gateware/rtl/raster/Makefile +++ b/gateware/rtl/raster/Makefile @@ -1,3 +1,8 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. +# # Makefile for tests and hardware verification. .PHONY: test clean diff --git a/gateware/rtl/raster/arty.xdc b/gateware/rtl/raster/arty.xdc deleted file mode 100644 index 07bc67e..0000000 --- a/gateware/rtl/raster/arty.xdc +++ /dev/null @@ -1,17 +0,0 @@ -# Clock pin -set_property PACKAGE_PIN E3 [get_ports {clk}] -set_property IOSTANDARD LVCMOS33 [get_ports {clk}] - -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] -set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1] -set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2] -set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3] -set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4] -set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] - -# Clock constraints -create_clock -period 10.0 [get_ports {clk}] diff --git a/gateware/rtl/raster/flow.json b/gateware/rtl/raster/flow.json deleted file mode 100644 index 7034f6b..0000000 --- a/gateware/rtl/raster/flow.json +++ /dev/null @@ -1,24 +0,0 @@ -{ - "default_part": "XC7A35TCSG324-1", - "values": { - "top": "top" - }, - "dependencies": { - "sources": [ - "synth_test_top.v", - "ram_fifo_dual_port.v", - "ram_fifo.v" - ], - "synth_log": "synth.log", - "pack_log": "pack.log" - }, - "XC7A35TCSG324-1": { - "default_target": "bitstream", - "dependencies": { - "build_dir": "build/arty_35", - "xdc": [ - "arty.xdc" - ] - } - } -} diff --git a/gateware/rtl/raster/ram_fifo.v b/gateware/rtl/raster/ram_fifo.v index 2fec37a..fbf00fc 100644 --- a/gateware/rtl/raster/ram_fifo.v +++ b/gateware/rtl/raster/ram_fifo.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Implements a synchronous(!) FIFO using inferred Block RAM. This * must wrap "ram_fifo_dual_port" due to difficulties YOSYS has with * inferring Block RAM: refer to that module for details. diff --git a/gateware/rtl/raster/ram_fifo_dual_port.v b/gateware/rtl/raster/ram_fifo_dual_port.v index c48890e..1d0e795 100644 --- a/gateware/rtl/raster/ram_fifo_dual_port.v +++ b/gateware/rtl/raster/ram_fifo_dual_port.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* YOSYS has a difficult time infering single port BRAM. It can infer * double-port block ram, however. This module is written as a double * port block ram, even though both clocks will end up being the same. diff --git a/gateware/rtl/raster/ram_fifo_sim.cpp b/gateware/rtl/raster/ram_fifo_sim.cpp index f42f661..158c55e 100644 --- a/gateware/rtl/raster/ram_fifo_sim.cpp +++ b/gateware/rtl/raster/ram_fifo_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/raster/ram_shim.v b/gateware/rtl/raster/ram_shim.v index 636ccb9..2d7b882 100644 --- a/gateware/rtl/raster/ram_shim.v +++ b/gateware/rtl/raster/ram_shim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Ram shim. This is an interface designed for a LiteX RAM DMA module. * It can also be connected to a simulator. * diff --git a/gateware/rtl/raster/ram_shim_cmds.vh b/gateware/rtl/raster/ram_shim_cmds.vh index 8cb3917..0ff3696 100644 --- a/gateware/rtl/raster/ram_shim_cmds.vh +++ b/gateware/rtl/raster/ram_shim_cmds.vh @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define RAM_SHIM_NO_OP 0 `define RAM_SHIM_WRITE_LOC 1 `define RAM_SHIM_WRITE_LEN 2 diff --git a/gateware/rtl/raster/ram_shim_sim.cpp b/gateware/rtl/raster/ram_shim_sim.cpp index a8fbb8e..6f8a3fd 100644 --- a/gateware/rtl/raster/ram_shim_sim.cpp +++ b/gateware/rtl/raster/ram_shim_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/raster/raster.v b/gateware/rtl/raster/raster.v index 1386f00..d3d2c61 100644 --- a/gateware/rtl/raster/raster.v +++ b/gateware/rtl/raster/raster.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Raster scanner. This module sweeps two DACs (the X and Y piezos) * across a box, where the X and Y axes may be at an angle. After * a single step, the ADCs connected to the raster scanner are diff --git a/gateware/rtl/raster/raster_cmds.vh b/gateware/rtl/raster/raster_cmds.vh index 8ae67c8..04bec00 100644 --- a/gateware/rtl/raster/raster_cmds.vh +++ b/gateware/rtl/raster/raster_cmds.vh @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define RASTER_NOOP 0 `define RASTER_MAX_SAMPLES 1 `define RASTER_MAX_LINES 2 diff --git a/gateware/rtl/raster/raster_sim.cpp b/gateware/rtl/raster/raster_sim.cpp index 81fb255..1ba5389 100644 --- a/gateware/rtl/raster/raster_sim.cpp +++ b/gateware/rtl/raster/raster_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/raster/raster_sim.v b/gateware/rtl/raster/raster_sim.v index e36478d..85a1b61 100644 --- a/gateware/rtl/raster/raster_sim.v +++ b/gateware/rtl/raster/raster_sim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `timescale 10ns/10ns `include "raster_cmds.vh" `include "ram_shim_cmds.vh" diff --git a/gateware/rtl/raster/script b/gateware/rtl/raster/script deleted file mode 100644 index 6714108..0000000 --- a/gateware/rtl/raster/script +++ /dev/null @@ -1,4 +0,0 @@ -read_verilog raster.v -synth_xilinx -flatten -nosrl -noclkbuf -nodsp -iopad -nowidelut -# synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut -write_verilog synth_test_yosys.v diff --git a/gateware/rtl/raster/synth_test_top.v b/gateware/rtl/raster/synth_test_top.v deleted file mode 100644 index 0cf97f9..0000000 --- a/gateware/rtl/raster/synth_test_top.v +++ /dev/null @@ -1,28 +0,0 @@ -module top ( - input clk, - input [1:0] btn, - input ck_io0, - input ck_io1, - input ck_io2, - input ck_io3, - output ck_io4, - output ck_io5, - output ck_io6, - output ck_io7, -); - - wire bufg; - BUFG bufgctrl ( - .I(clk), - .O(bufg) - ); - - ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf ( - .clk(bufg), - .rst(0), - .read_enable(btn[0]), - .write_enable(btn[1]), - .write_dat({ck_io0,ck_io1,ck_io2,ck_io3}), - .read_dat({ck_io4,ck_io5,ck_io6,ck_io7}) - ); -endmodule diff --git a/gateware/rtl/spi/Makefile b/gateware/rtl/spi/Makefile index 7078106..aebf15d 100644 --- a/gateware/rtl/spi/Makefile +++ b/gateware/rtl/spi/Makefile @@ -1,3 +1,7 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. # Makefile for tests and hardware verification. .PHONY: test clean codegen diff --git a/gateware/rtl/spi/ramp.v b/gateware/rtl/spi/ramp.v index 3fedd7e..f3fdd95 100644 --- a/gateware/rtl/spi/ramp.v +++ b/gateware/rtl/spi/ramp.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Dynamically adjustable DAC ramping. * Given an increment voltage and a speed setting, increase the voltage * to that voltage in increments over a period of time. diff --git a/gateware/rtl/spi/spi_master.v b/gateware/rtl/spi/spi_master.v index 82463c2..65478d2 100644 --- a/gateware/rtl/spi/spi_master.v +++ b/gateware/rtl/spi/spi_master.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* (c) Peter McGoron 2022 v0.3 * This Source Code Form is subject to the terms of the Mozilla Public * License, v.2.0. If a copy of the MPL was not distributed with this diff --git a/gateware/rtl/spi/spi_master_no_read.v b/gateware/rtl/spi/spi_master_no_read.v index 0999807..61704b4 100644 --- a/gateware/rtl/spi/spi_master_no_read.v +++ b/gateware/rtl/spi/spi_master_no_read.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_MASTER_NO_READ /* verilator lint_off DECLFILENAME */ `include "spi_master.v" diff --git a/gateware/rtl/spi/spi_master_no_write.v b/gateware/rtl/spi/spi_master_no_write.v index 31f8b5c..e18a5bb 100644 --- a/gateware/rtl/spi/spi_master_no_write.v +++ b/gateware/rtl/spi/spi_master_no_write.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_MASTER_NO_WRITE /* verilator lint_off DECLFILENAME */ `include "spi_master.v" diff --git a/gateware/rtl/spi/spi_master_ss.v b/gateware/rtl/spi/spi_master_ss.v index 6dc3429..32c7139 100644 --- a/gateware/rtl/spi/spi_master_ss.v +++ b/gateware/rtl/spi/spi_master_ss.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_MASTER_SS_NAME spi_master_ss `define SPI_MASTER_NAME spi_master /* verilator lint_off DECLFILENAME */ diff --git a/gateware/rtl/spi/spi_master_ss_no_read.v b/gateware/rtl/spi/spi_master_ss_no_read.v index 741e940..3096528 100644 --- a/gateware/rtl/spi/spi_master_ss_no_read.v +++ b/gateware/rtl/spi/spi_master_ss_no_read.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_MASTER_SS_NAME spi_master_ss_no_read `define SPI_MASTER_NAME spi_master_no_read `define SPI_MASTER_NO_READ diff --git a/gateware/rtl/spi/spi_master_ss_no_write.v b/gateware/rtl/spi/spi_master_ss_no_write.v index 9be3e7f..5a0b2ff 100644 --- a/gateware/rtl/spi/spi_master_ss_no_write.v +++ b/gateware/rtl/spi/spi_master_ss_no_write.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_MASTER_SS_NAME spi_master_ss_no_write `define SPI_MASTER_NAME spi_master_no_write `define SPI_MASTER_NO_WRITE diff --git a/gateware/rtl/spi/spi_master_ss_template.v b/gateware/rtl/spi/spi_master_ss_template.v index fff9d08..26c18e7 100644 --- a/gateware/rtl/spi/spi_master_ss_template.v +++ b/gateware/rtl/spi/spi_master_ss_template.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* (c) Peter McGoron 2022 v0.3 * This Source Code Form is subject to the terms of the Mozilla Public * License, v.2.0. If a copy of the MPL was not distributed with this diff --git a/gateware/rtl/spi/spi_slave.v b/gateware/rtl/spi/spi_slave.v index 4628a9f..9323b60 100644 --- a/gateware/rtl/spi/spi_slave.v +++ b/gateware/rtl/spi/spi_slave.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* (c) Peter McGoron 2022 v0.3 * This Source Code Form is subject to the terms of the Mozilla Public * License, v.2.0. If a copy of the MPL was not distributed with this diff --git a/gateware/rtl/spi/spi_slave_no_read.v b/gateware/rtl/spi/spi_slave_no_read.v index 12705b9..712f781 100644 --- a/gateware/rtl/spi/spi_slave_no_read.v +++ b/gateware/rtl/spi/spi_slave_no_read.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_SLAVE_NO_READ /* verilator lint_off DECLFILENAME */ `include "spi_slave.v" diff --git a/gateware/rtl/spi/spi_slave_no_write.v b/gateware/rtl/spi/spi_slave_no_write.v index f60ea0b..156b536 100644 --- a/gateware/rtl/spi/spi_slave_no_write.v +++ b/gateware/rtl/spi/spi_slave_no_write.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ `define SPI_SLAVE_NO_WRITE /* verilator lint_off DECLFILENAME */ `include "spi_slave.v" diff --git a/gateware/rtl/spi/spi_switch.v b/gateware/rtl/spi/spi_switch.v index 2136288..ca9dbed 100644 --- a/gateware/rtl/spi/spi_switch.v +++ b/gateware/rtl/spi/spi_switch.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* This module is a co-operative crossbar for the wires only. Each end * implements its own SPI master. * diff --git a/gateware/rtl/spi/spi_switch_sim.cpp b/gateware/rtl/spi/spi_switch_sim.cpp index f904dc4..cc58ee9 100644 --- a/gateware/rtl/spi/spi_switch_sim.cpp +++ b/gateware/rtl/spi/spi_switch_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include "../util.hpp" #include "Vspi_switch.h" Vspi_switch *tb; diff --git a/gateware/rtl/testbench.hpp b/gateware/rtl/testbench.hpp index b2f7eb5..766ae52 100644 --- a/gateware/rtl/testbench.hpp +++ b/gateware/rtl/testbench.hpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #pragma once #include #include "util.hpp" diff --git a/gateware/rtl/util.hpp b/gateware/rtl/util.hpp index c6ca40a..803670b 100644 --- a/gateware/rtl/util.hpp +++ b/gateware/rtl/util.hpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #pragma once #include #include diff --git a/gateware/rtl/waveform/Makefile b/gateware/rtl/waveform/Makefile index 9093464..e61c444 100644 --- a/gateware/rtl/waveform/Makefile +++ b/gateware/rtl/waveform/Makefile @@ -1,3 +1,8 @@ +# Copyright 2023 (C) Peter McGoron +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. + # Makefile for tests and hardware verification. include ../common.makefile diff --git a/gateware/rtl/waveform/bram_dma.cpp b/gateware/rtl/waveform/bram_dma.cpp index 3bd2238..76c17c1 100644 --- a/gateware/rtl/waveform/bram_dma.cpp +++ b/gateware/rtl/waveform/bram_dma.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include "bram_dma.hpp" #include "../util.hpp" #include diff --git a/gateware/rtl/waveform/bram_dma.hpp b/gateware/rtl/waveform/bram_dma.hpp index b3f982b..f3381a2 100644 --- a/gateware/rtl/waveform/bram_dma.hpp +++ b/gateware/rtl/waveform/bram_dma.hpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #pragma once #include diff --git a/gateware/rtl/waveform/bram_interface.v b/gateware/rtl/waveform/bram_interface.v index 289d875..0f8f045 100644 --- a/gateware/rtl/waveform/bram_interface.v +++ b/gateware/rtl/waveform/bram_interface.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ module bram_interface #( parameter WORD_WID = 24, parameter WORD_AMNT_WID = 11, diff --git a/gateware/rtl/waveform/bram_interface_sim.cpp b/gateware/rtl/waveform/bram_interface_sim.cpp index c0074b8..58abec9 100644 --- a/gateware/rtl/waveform/bram_interface_sim.cpp +++ b/gateware/rtl/waveform/bram_interface_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ #include #include #include diff --git a/gateware/rtl/waveform/bram_interface_sim.v b/gateware/rtl/waveform/bram_interface_sim.v index cec32cd..ad84b89 100644 --- a/gateware/rtl/waveform/bram_interface_sim.v +++ b/gateware/rtl/waveform/bram_interface_sim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ module bram_interface_sim #( parameter WORD_WID = 20, parameter WORD_AMNT_WID = 11, diff --git a/gateware/rtl/waveform/dma_sim.v b/gateware/rtl/waveform/dma_sim.v index b2f44d1..5abb44f 100644 --- a/gateware/rtl/waveform/dma_sim.v +++ b/gateware/rtl/waveform/dma_sim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* This module is used to simulate direct memory access, where only * a small amount of memory is valid to read. */ diff --git a/gateware/rtl/waveform/waveform.v b/gateware/rtl/waveform/waveform.v index de261c9..ce18ff5 100644 --- a/gateware/rtl/waveform/waveform.v +++ b/gateware/rtl/waveform/waveform.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* Write a waveform to a DAC. */ /* TODO: Add "how many values to go" counter. */ module waveform #( diff --git a/gateware/rtl/waveform/waveform_sim.cpp b/gateware/rtl/waveform/waveform_sim.cpp index 9cc2924..9663163 100644 --- a/gateware/rtl/waveform/waveform_sim.cpp +++ b/gateware/rtl/waveform/waveform_sim.cpp @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ /* TODO: impleement reset for dma and test both separetely */ #include #include "Vwaveform_sim.h" diff --git a/gateware/rtl/waveform/waveform_sim.v b/gateware/rtl/waveform/waveform_sim.v index 09b4f0b..6ed09eb 100644 --- a/gateware/rtl/waveform/waveform_sim.v +++ b/gateware/rtl/waveform/waveform_sim.v @@ -1,3 +1,8 @@ +/* Copyright 2023 (C) Peter McGoron + * This file is a part of Upsilon, a free and open source software project. + * For license terms, refer to the files in `doc/copying` in the Upsilon + * source distribution. + */ module waveform_sim #( parameter DAC_WID = 24, parameter DAC_WID_SIZ = 5, diff --git a/gateware/soc.py b/gateware/soc.py index 3dd9302..9c24de5 100644 --- a/gateware/soc.py +++ b/gateware/soc.py @@ -1,3 +1,4 @@ +""" ########################################################################## # Portions of this file incorporate code licensed under the # BSD 2-Clause License. @@ -32,6 +33,12 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ########################################################################## +# Copyright 2023 (C) Peter McGoron +# +# This file is a part of Upsilon, a free and open source software project. +# For license terms, refer to the files in `doc/copying` in the Upsilon +# source distribution. +""" # There is nothing fundamental about the Arty A7(35|100)T to this # design, but another eval board will require some porting. diff --git a/opensbi/litex/vexriscv/Kconfig b/opensbi/litex/vexriscv/Kconfig index 806d366..2c48861 100644 --- a/opensbi/litex/vexriscv/Kconfig +++ b/opensbi/litex/vexriscv/Kconfig @@ -1,4 +1,5 @@ # SPDX-License-Identifier: BSD-2-Clause +# Copyright 2023 (C) Peter McGoron config PLATFORM_LITEX_VEXRISCV bool diff --git a/opensbi/litex/vexriscv/configs/defconfig b/opensbi/litex/vexriscv/configs/defconfig index 90c2343..d93a335 100644 --- a/opensbi/litex/vexriscv/configs/defconfig +++ b/opensbi/litex/vexriscv/configs/defconfig @@ -3,6 +3,7 @@ # # Copyright (c) 2020 Florent Kermarrec # Copyright (c) 2020 Dolu1990 +# Copyright (c) 2023 Peter McGoron # # Command for platform specific "make run" diff --git a/opensbi/litex/vexriscv/objects.mk b/opensbi/litex/vexriscv/objects.mk index 3587e7b..9d59a57 100644 --- a/opensbi/litex/vexriscv/objects.mk +++ b/opensbi/litex/vexriscv/objects.mk @@ -3,6 +3,7 @@ # # Copyright (c) 2020 Florent Kermarrec # Copyright (c) 2020 Dolu1990 +# Copyright (c) 2023 Peter McGoron # # Command for platform specific "make run" diff --git a/opensbi/litex/vexriscv/platform.c b/opensbi/litex/vexriscv/platform.c index 54e23b7..c59c906 100644 --- a/opensbi/litex/vexriscv/platform.c +++ b/opensbi/litex/vexriscv/platform.c @@ -2,6 +2,7 @@ * SPDX-License-Identifier: BSD-2-Clause * * Copyright (c) 2020 Dolu1990 + * Copyright (C) 2023 Peter McGoron * */