From 33ec8351d83a6a79dbcd5a792fb9d37e96717146 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Thu, 24 Nov 2022 09:48:04 -0500 Subject: [PATCH] correctly (and crudely) simulate control loop Issue was that the ADC cycle half wait (SCK delay) was too fast for the input buffering (since MISO and MOSI are physical inputs and not FPGA wires). --- firmware/rtl/control_loop/control_loop.v | 4 ++-- .../rtl/control_loop/control_loop_sim.cpp | 20 ++++++++++++++----- firmware/rtl/spi/spi_slave.v | 11 +++++++--- 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/firmware/rtl/control_loop/control_loop.v b/firmware/rtl/control_loop/control_loop.v index a289842..bef62a2 100644 --- a/firmware/rtl/control_loop/control_loop.v +++ b/firmware/rtl/control_loop/control_loop.v @@ -4,8 +4,8 @@ module control_loop #( parameter ADC_WID = 18, parameter ADC_WID_SIZ = 5, - parameter ADC_CYCLE_HALF_WAIT = 1, - parameter ADC_CYCLE_HALF_WAIT_SIZ = 1, + parameter ADC_CYCLE_HALF_WAIT = 5, + parameter ADC_CYCLE_HALF_WAIT_SIZ = 3, parameter ADC_POLARITY = 1, parameter ADC_PHASE = 0, /* The ADC takes maximum 527 ns to capture a value. diff --git a/firmware/rtl/control_loop/control_loop_sim.cpp b/firmware/rtl/control_loop/control_loop_sim.cpp index cdc4d53..9d208ab 100644 --- a/firmware/rtl/control_loop/control_loop_sim.cpp +++ b/firmware/rtl/control_loop/control_loop_sim.cpp @@ -52,18 +52,20 @@ int main(int argc, char **argv) { mod->clk = 0; - set_value(10000, CONTROL_LOOP_STATUS); set_value(0b11010111000010100011110101110000101000111, CONTROL_LOOP_P); - set_value((V)12 << CONSTS_FRAC, CONTROL_LOOP_I); + set_value((V)6 << CONSTS_FRAC, CONTROL_LOOP_I); set_value(20, CONTROL_LOOP_DELAY); set_value(10000, CONTROL_LOOP_SETPT); set_value(1, CONTROL_LOOP_STATUS); + mod->curset = 0; - for (int tick = 0; tick < 100000; tick++) { - std::cout << tick << std::endl; + for (int tick = 0; tick < 500000; tick++) { run_clock(); if (mod->request && !mod->fulfilled) { - mod->measured_value = func.val(mod->curset); + V ext = sign_extend(mod->curset, 20); + V val = func.val(ext); + printf("setting: %ld, val: %ld\n", ext, val); + mod->measured_value = val; mod->fulfilled = 1; } else if (mod->fulfilled && !mod->request) { mod->fulfilled = 0; @@ -73,6 +75,14 @@ int main(int argc, char **argv) { mod->cmd = CONTROL_LOOP_WRITE_BIT | CONTROL_LOOP_P; mod->word_into_loop = 0b010111000010100011110101110000101000111; mod->start_cmd = 1; + printf("adjust P\n"); + } + if (tick == 100000) { + mod->cmd = CONTROL_LOOP_WRITE_BIT | CONTROL_LOOP_I; + /* 0.5 */ + mod->word_into_loop = 1 << (CONSTS_FRAC - 1); + printf("adjust I\n"); + mod->start_cmd = 1; } if (mod->finish_cmd) { mod->start_cmd = 0; diff --git a/firmware/rtl/spi/spi_slave.v b/firmware/rtl/spi/spi_slave.v index bf7445d..5ef89af 100644 --- a/firmware/rtl/spi/spi_slave.v +++ b/firmware/rtl/spi/spi_slave.v @@ -138,9 +138,14 @@ always @ (posedge clk) begin default: ; endcase end - 2'b00: if (!rdy) begin - finished <= 0; - err <= 0; + 2'b00: begin + if (!rdy) begin + finished <= 0; + err <= 0; + end +`ifndef SPI_SLAVE_NO_WRITE + miso <= 0; +`endif end endcase end