reorganize litex code
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Copyright 2024 (C) Peter McGoron.
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This file is a part of Upsilon, a free and open source software project.
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For license terms, refer to the files in ``doc/copying`` in the Upsilon
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source distribution.
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***************************************************
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====================
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System Within a Chip
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====================
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A *system within a chip* (SWiC) is a SoC within a SoC. Upsilon has the
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capability to add SWiCs that can be controlled by the main CPU. The CPU for
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the SWiC is the PicoRV32, which is a RISC-V RVI32 core with optional C, M
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extensions and custom-made non-branching instructions.
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----------------
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Main CPU Control
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----------------
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The main CPU controls the SWiC using two methods:
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1. LiteX CSR Registers. This is for simple things where the main CPU should
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have 100% control at all times, like starting and stopping the CPU.
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2. *Preemptive interfaces* (PI), which sit in front of a Wishbone slave. The
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main CPU has a LiteX CSR register which selects the Wishbone master the
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Wishbone slave connects to.
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In usual operation the SWiC RAM sits behind a PI. Before the SWiC starts, the
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main CPU switches the PI to itself, fills the RAM with the program, and then
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switches it back to the SWiC. When the SWiC starts, the SWiC has read-write
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access to the RAM. PIs are also used for connecting to external IO (like SPI).
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In the future, there will be master-read-slave-write interfaces to transfer
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bulk memory from the SWiC to the main CPU (for instances, raster scanning).
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See /gateware/soc.py for implementation notes.
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@ -0,0 +1,75 @@
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# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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from migen import *
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from litex.soc.interconnect.wishbone import Interface
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from util import *
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class SPIMaster(Module):
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""" Wrapper for the SPI master verilog code. """
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def __init__(self, rst, miso, mosi, sck, ss,
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polarity = 0,
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phase = 0,
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ss_wait = 1,
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enable_miso = 1,
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enable_mosi = 1,
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spi_wid = 24,
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spi_cycle_half_wait = 1,
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):
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"""
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:param rst: Reset signal.
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:param miso: MISO signal.
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:param mosi: MOSI signal.
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:param sck: SCK signal.
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:param ss: SS signal.
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:param phase: Phase of SPI master. This phase is not the standard
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SPI phase because it is defined in terms of the rising edge, not
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the leading edge. See <https://software.mcgoron.com/peter/spi>
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:param polarity: See <https://software.mcgoron.com/peter/spi>.
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:param enable_miso: If ``False``, the module does not read data
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from MISO into a register.
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:param enable_mosi: If ``False``, the module does not write data
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to MOSI from a register.
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:param spi_wid: Verilog parameter: see file.
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:param spi_cycle_half_wait: Verilog parameter: see file.
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"""
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self.bus = Interface(data_width = 32, address_width=32, addressing="word")
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self.addr_space_size = 0x10
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self.comb += [
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self.bus.err.eq(0),
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]
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self.specials += Instance("spi_master_ss_wb",
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p_SS_WAIT = ss_wait,
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p_SS_WAIT_TIMER_LEN = minbits(ss_wait),
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p_CYCLE_HALF_WAIT = spi_cycle_half_wait,
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p_TIMER_LEN = minbits(spi_cycle_half_wait),
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p_WID = spi_wid,
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p_WID_LEN = minbits(spi_wid),
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p_ENABLE_MISO = enable_miso,
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p_ENABLE_MOSI = enable_mosi,
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p_POLARITY = polarity,
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p_PHASE = phase,
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i_clk = ClockSignal(),
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i_rst_L = rst,
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i_miso = miso,
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o_mosi = mosi,
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o_sck_wire = sck,
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o_ss_L = ss,
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i_wb_cyc = self.bus.cyc,
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i_wb_stb = self.bus.stb,
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i_wb_we = self.bus.we,
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i_wb_sel = self.bus.sel,
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i_wb_addr = self.bus.adr,
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i_wb_dat_w = self.bus.dat_w,
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o_wb_ack = self.bus.ack,
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o_wb_dat_r = self.bus.dat_r,
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)
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@ -0,0 +1,83 @@
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# Copyright 2023-2024 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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from migen import *
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from litex.soc.interconnect.wishbone import Decoder
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from util import *
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"""
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LiteX has an automatic Wishbone bus generator that has a lot of quality of life
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features, like overlap checking, relocation, multiple masters, etc.
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It doesn't work when the main SoC bus is also using the bus generator, so this
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module implements a basic Wishbone bus generator. All locations have to be
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added manually and there is no sanity checking.
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"""
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class BasicRegion:
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""" Simple class for storing a RAM region. """
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def __init__(self, origin, size, bus=None):
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"""
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:param origin: Positive integer denoting the start location
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of the memory region.
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:param size: Size of the memory region. This must be of the form
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(2**N - 1).
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:param bus: Instance of a wishbone bus interface.
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"""
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self.origin = origin
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self.size = size
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self.bus = bus
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def decoder(self):
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"""
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Wishbone decoder generator. The decoder looks at the high
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bits of the address to check what bits are passed to the
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slave device.
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Examples:
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Location 0x10000 has 0xFFFF of address space.
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origin = 0x10000, rightbits = 16.
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Location 0x10000 has 0xFFF of address space.
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origin = 0x10000, rightbits = 12.
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Location 0x100000 has 0x1F of address space.
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origin = 0x100000, rightbits = 5.
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"""
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rightbits = minbits(self.size-1)
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print(self.origin, self.origin >> rightbits)
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return lambda addr: addr[rightbits:32] == (self.origin >> rightbits)
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def to_dict(self):
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return {"origin" : self.origin, "size": self.size}
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def __str__(self):
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return str(self.to_dict())
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class MemoryMap:
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""" Stores the memory map of an embedded core. """
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def __init__(self):
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self.regions = {}
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def add_region(self, name, region):
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assert name not in self.regions
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self.regions[name] = region
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def dump_mmap(self, jsonfile):
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with open(jsonfile, 'wt') as f:
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import json
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json.dump({k : self.regions[k].to_dict() for k in self.regions}, f)
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def bus_submodule(self, masterbus):
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""" Return a module that decodes the masterbus into the
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slave devices according to their origin and start positions. """
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slaves = [(self.regions[n].decoder(), self.regions[n].bus)
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for n in self.regions]
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return Decoder(masterbus, slaves, register=False)
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335
gateware/soc.py
335
gateware/soc.py
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@ -60,11 +60,9 @@ from litedram.modules import MT41K128M16
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from litedram.frontend.dma import LiteDRAMDMAReader
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from liteeth.phy.mii import LiteEthPHYMII
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from math import log2, floor
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def minbits(n):
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""" Return the amount of bits necessary to store n. """
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return floor(log2(n) + 1)
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from util import *
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from swic import *
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from extio import *
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"""
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Keep this diagram up to date! This is the wiring diagram from the ADC to
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@ -93,6 +91,8 @@ generator. These pins are then connected to Verilog modules.
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If there is more than one pin in the Pins string, the resulting
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name will be a vector of pins.
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TODO: generate declaratively from constraints file.
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"""
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io = [
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# ("differntial_output_low", 0, Pins("J17 J18 K15 J15 U14 V14 T13 U13 B6 E5 A3"), IOStandard("LVCMOS33")),
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@ -111,318 +111,6 @@ io = [
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# ("test_clock", 0, Pins("P18"), IOStandard("LVCMOS33"))
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]
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class PreemptiveInterface(Module, AutoCSR):
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""" A preemptive interface is a manually controlled Wishbone interface
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that stands between multiple masters (potentially interconnects) and a
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single slave. A master controls which master (or interconnect) has access
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to the slave. This is to avoid bus contention by having multiple buses. """
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def __init__(self, masters_len, slave):
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"""
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:param masters_len: The amount of buses accessing this slave. This number
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must be greater than one.
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:param slave: The slave device. This object must have an Interface object
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accessable as ``bus``.
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"""
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assert masters_len > 1
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self.buses = []
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self.master_select = CSRStorage(masters_len, name='master_select', description='RW bitstring of which master interconnect to connect to')
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self.slave = slave
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for i in range(masters_len):
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# Add the slave interface each master interconnect sees.
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self.buses.append(Interface(data_width=32, address_width=32, addressing="byte"))
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"""
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Construct a combinatorial case statement. In verilog, the if
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statment would look like
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always @ (*) case (master_select)
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1: begin
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// Bus assignments...
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end
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2: begin
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// Bus assignments...
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end
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// more cases:
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default:
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// assign everything to master 0
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end
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The If statement in Migen (Python HDL) is an object with a method
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called "ElseIf" and "Else", that return objects with the specified
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case attached. Instead of directly writing an If statement into
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the combinatorial block, the If statement is constructed in a
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for loop.
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Avoiding latches:
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Left hand sign (assignment) is always an input.
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"""
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def assign_for_case(current_case):
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asn = [ ]
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for j in range(masters_len):
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if current_case == j:
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asn += [
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self.slave.bus.adr.eq(self.buses[j].adr),
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self.slave.bus.dat_w.eq(self.buses[j].dat_w),
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self.slave.bus.cyc.eq(self.buses[j].cyc),
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self.slave.bus.stb.eq(self.buses[j].stb),
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self.slave.bus.we.eq(self.buses[j].we),
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self.slave.bus.sel.eq(self.buses[j].sel),
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self.buses[j].dat_r.eq(self.slave.bus.dat_r),
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self.buses[j].ack.eq(self.slave.bus.ack),
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]
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else:
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asn += [
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self.buses[j].dat_r.eq(0),
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self.buses[j].ack.eq(self.buses[j].cyc & self.buses[j].stb),
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]
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return asn
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cases = {"default": assign_for_case(0)}
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for i in range(1, masters_len):
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cases[i] = assign_for_case(i)
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self.comb += Case(self.master_select.storage, cases)
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class SPIMaster(Module):
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""" Wrapper for the SPI master verilog code. """
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def __init__(self, rst, miso, mosi, sck, ss,
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polarity = 0,
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phase = 0,
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ss_wait = 1,
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enable_miso = 1,
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enable_mosi = 1,
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spi_wid = 24,
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spi_cycle_half_wait = 1,
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):
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"""
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:param rst: Reset signal.
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:param miso: MISO signal.
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:param mosi: MOSI signal.
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:param sck: SCK signal.
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:param ss: SS signal.
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:param phase: Phase of SPI master. This phase is not the standard
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SPI phase because it is defined in terms of the rising edge, not
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the leading edge. See <https://software.mcgoron.com/peter/spi>
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:param polarity: See <https://software.mcgoron.com/peter/spi>.
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:param enable_miso: If ``False``, the module does not read data
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from MISO into a register.
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:param enable_mosi: If ``False``, the module does not write data
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to MOSI from a register.
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:param spi_wid: Verilog parameter: see file.
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:param spi_cycle_half_wait: Verilog parameter: see file.
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"""
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self.bus = Interface(data_width = 32, address_width=32, addressing="word")
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self.region = SoCRegion(size=0x10, cached=False)
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self.comb += [
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self.bus.err.eq(0),
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]
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self.specials += Instance("spi_master_ss_wb",
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p_SS_WAIT = ss_wait,
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p_SS_WAIT_TIMER_LEN = minbits(ss_wait),
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p_CYCLE_HALF_WAIT = spi_cycle_half_wait,
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p_TIMER_LEN = minbits(spi_cycle_half_wait),
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p_WID = spi_wid,
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p_WID_LEN = minbits(spi_wid),
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p_ENABLE_MISO = enable_miso,
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p_ENABLE_MOSI = enable_mosi,
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p_POLARITY = polarity,
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p_PHASE = phase,
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i_clk = ClockSignal(),
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i_rst_L = rst,
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i_miso = miso,
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o_mosi = mosi,
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o_sck_wire = sck,
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o_ss_L = ss,
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i_wb_cyc = self.bus.cyc,
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i_wb_stb = self.bus.stb,
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i_wb_we = self.bus.we,
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i_wb_sel = self.bus.sel,
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i_wb_addr = self.bus.adr,
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i_wb_dat_w = self.bus.dat_w,
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o_wb_ack = self.bus.ack,
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o_wb_dat_r = self.bus.dat_r,
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)
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#TODO: Generalize CSR stuff
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class ControlLoopParameters(Module, AutoCSR):
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""" Interface for the Linux CPU to write parameters to the CPU
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and for the CPU to write data back to the CPU without complex
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locking mechanisms.
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"""
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def __init__(self):
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self.cl_I = CSRStorage(32, description='Integral parameter')
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self.cl_P = CSRStorage(32, description='Proportional parameter')
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self.deltaT = CSRStorage(32, description='Wait parameter')
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self.setpt = CSRStorage(32, description='Setpoint')
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self.zset = CSRStatus(32, description='Set Z position')
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self.zpos = CSRStatus(32, description='Measured Z position')
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self.bus = Interface(data_width = 32, address_width = 32, addressing="word")
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self.width = 0x20
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self.sync += [
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If(self.bus.cyc == 1 and self.bus.stb == 1 and self.bus.ack == 0,
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Case(self.bus.adr[0:4], {
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0x0: self.bus.dat_r.eq(self.cl_I.storage),
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0x4: self.bus.dat_r.eq(self.cl_P.storage),
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0x8: self.bus.dat_r.eq(self.deltaT.storage),
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0xC: self.bus.dat_r.eq(self.setpt.storage),
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0x10: If(self.bus.we,
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self.zset.status.eq(self.bus.dat_w)
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).Else(
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self.bus.dat_r.eq(self.zset.status)
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),
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0x14: If(self.bus.we,
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self.zpos.status.eq(self.bus.dat_w),
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).Else(
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self.bus.dat_r.eq(self.zpos.status)
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),
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"default": self.bus.dat_r.eq(0xdeadbeef),
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}),
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self.bus.ack.eq(1),
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).Else(
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self.bus.ack.eq(0),
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)
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]
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class BasicRegion:
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""" Simple class for storing a RAM region. """
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def __init__(self, origin, size, bus=None):
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self.origin = origin
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self.size = size
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self.bus = bus
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def decoder(self):
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"""
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Wishbone decoder generator. The decoder looks at the high
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bits of the address to check what bits are passed to the
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slave device.
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|
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Examples:
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|
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Location 0x10000 has 0xFFFF of address space.
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origin = 0x10000, rightbits = 16.
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Location 0x10000 has 0xFFF of address space.
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origin = 0x10000, rightbits = 12.
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Location 0x100000 has 0x1F of address space.
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origin = 0x100000, rightbits = 5.
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"""
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rightbits = minbits(self.size-1)
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print(self.origin, self.origin >> rightbits)
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return lambda addr: addr[rightbits:32] == (self.origin >> rightbits)
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def to_dict(self):
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return {"origin" : self.origin, "size": self.size}
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def __str__(self):
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return str(self.to_dict())
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class MemoryMap:
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""" Stores the memory map of an embedded core. """
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def __init__(self):
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self.regions = {}
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def add_region(self, name, region):
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assert name not in self.regions
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self.regions[name] = region
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def dump_json(self, jsonfile):
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with open(jsonfile, 'wt') as f:
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import json
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json.dump({k : self.regions[k].to_dict() for k in self.regions}, f)
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|
||||
def bus_submodule(self, masterbus):
|
||||
""" Return a module that decodes the masterbus into the
|
||||
slave devices according to their origin and start positions. """
|
||||
slaves = [(self.regions[n].decoder(), self.regions[n].bus)
|
||||
for n in self.regions]
|
||||
return Decoder(masterbus, slaves, register=False)
|
||||
|
||||
class PicoRV32(Module, AutoCSR):
|
||||
def add_ram(self, name, width, origin):
|
||||
mod = SRAM(width)
|
||||
self.submodules += mod
|
||||
|
||||
self.mmap.add_region(name, BasicRegion(width, origin, mod.bus))
|
||||
|
||||
def add_params(self, origin):
|
||||
self.submodules.params = params = ControlLoopParameters()
|
||||
self.mmap.add_region('params', BasicRegion(origin, params.width, params.bus))
|
||||
|
||||
def __init__(self, name, start_addr=0x10000, irq_addr=0x10010):
|
||||
self.mmap = MemoryMap()
|
||||
self.name = name
|
||||
|
||||
self.masterbus = Interface(data_width=32, address_width=32, addressing="byte")
|
||||
|
||||
self.resetpin = CSRStorage(1, name="enable", description="PicoRV32 enable")
|
||||
|
||||
self.trap = CSRStatus(8, name="trap", description="Trap condition")
|
||||
self.d_adr = CSRStatus(32)
|
||||
self.d_dat_w = CSRStatus(32)
|
||||
self.dbg_insn_addr = CSRStatus(32)
|
||||
self.dbg_insn_opcode = CSRStatus(32)
|
||||
|
||||
self.comb += [
|
||||
self.d_adr.status.eq(self.masterbus.adr),
|
||||
self.d_dat_w.status.eq(self.masterbus.dat_w),
|
||||
]
|
||||
|
||||
# NOTE: need to compile to these extact instructions
|
||||
self.specials += Instance("picorv32_wb",
|
||||
p_COMPRESSED_ISA = 1,
|
||||
p_ENABLE_MUL = 1,
|
||||
p_PROGADDR_RESET=start_addr,
|
||||
p_PROGADDR_IRQ =irq_addr,
|
||||
p_REGS_INIT_ZERO = 1,
|
||||
o_trap = self.trap.status,
|
||||
|
||||
i_wb_rst_i = ~self.resetpin.storage,
|
||||
i_wb_clk_i = ClockSignal(),
|
||||
o_wbm_adr_o = self.masterbus.adr,
|
||||
o_wbm_dat_o = self.masterbus.dat_r,
|
||||
i_wbm_dat_i = self.masterbus.dat_w,
|
||||
o_wbm_we_o = self.masterbus.we,
|
||||
o_wbm_sel_o = self.masterbus.sel,
|
||||
o_wbm_stb_o = self.masterbus.stb,
|
||||
i_wbm_ack_i = self.masterbus.ack,
|
||||
o_wbm_cyc_o = self.masterbus.cyc,
|
||||
|
||||
o_pcpi_valid = Signal(),
|
||||
o_pcpi_insn = Signal(32),
|
||||
o_pcpi_rs1 = Signal(32),
|
||||
o_pcpi_rs2 = Signal(32),
|
||||
i_pcpi_wr = 0,
|
||||
i_pcpi_wait = 0,
|
||||
i_pcpi_rd = 0,
|
||||
i_pcpi_ready = 0,
|
||||
|
||||
i_irq = 0,
|
||||
o_eoi = Signal(32),
|
||||
|
||||
o_trace_valid = Signal(),
|
||||
o_trace_data = Signal(36),
|
||||
o_debug_state = Signal(2),
|
||||
|
||||
o_dbg_insn_addr = self.dbg_insn_addr.status,
|
||||
o_dbg_insn_opcode = self.dbg_insn_opcode.status,
|
||||
)
|
||||
|
||||
def do_finalize(self):
|
||||
self.mmap.dump_json(self.name + ".json")
|
||||
self.submodules.decoder = self.mmap.bus_submodule(self.masterbus)
|
||||
|
||||
# Clock and Reset Generator
|
||||
# I don't know how this works, I only know that it does.
|
||||
class _CRG(Module):
|
||||
|
|
@ -462,9 +150,8 @@ class UpsilonSoC(SoCCore):
|
|||
self.add_constant(f"{ip_name}{seg_num}", int(ip_byte))
|
||||
|
||||
def add_blockram(self, name, size, connect_now=True):
|
||||
assert not hasattr(self.submodules, name)
|
||||
mod = SRAM(size)
|
||||
setattr(self.submodules, name, mod)
|
||||
self.add_module(name, mod)
|
||||
|
||||
if connect_now:
|
||||
self.bus.add_slave(name, mod.bus,
|
||||
|
|
@ -472,19 +159,17 @@ class UpsilonSoC(SoCCore):
|
|||
return mod
|
||||
|
||||
def add_preemptive_interface(self, name, size, slave):
|
||||
assert not hasattr(self.submodules, name)
|
||||
mod = PreemptiveInterface(size, slave)
|
||||
setattr(self.submodules, name, mod)
|
||||
self.add_module(name, mod)
|
||||
return mod
|
||||
|
||||
def add_picorv32(self, name, size=0x1000, origin=0x10000, param_origin=0x100000):
|
||||
assert not hasattr(self.submodules, name)
|
||||
pico = PicoRV32(name, origin, origin+0x10)
|
||||
setattr(self.submodules, name, pico)
|
||||
self.add_module(name, pico)
|
||||
|
||||
ram = self.add_blockram(name + "_ram", size=size, connect_now=False)
|
||||
ram_iface = self.add_preemptive_interface(name + "ram_iface", 2, ram)
|
||||
pico.mmap.add_region("main",
|
||||
pico.add_region("main",
|
||||
BasicRegion(origin=origin, size=size, bus=ram_iface.buses[1]))
|
||||
|
||||
self.bus.add_slave(name + "_ram", ram_iface.buses[0],
|
||||
|
|
@ -573,7 +258,7 @@ class UpsilonSoC(SoCCore):
|
|||
platform.request("dac_sck_0"),
|
||||
platform.request("dac_ss_L_0"),
|
||||
)
|
||||
self.bus.add_slave("spi0", self.spi0.bus, self.spi0.region)
|
||||
self.bus.add_slave("spi0", self.spi0.bus, SoCRegion(origin=None, size=self.spi0.addr_space_size, cached=False))
|
||||
|
||||
self.add_picorv32("pico0")
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,206 @@
|
|||
# Copyright 2023-2024 (C) Peter McGoron
|
||||
#
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
||||
from migen import *
|
||||
from litex.soc.interconnect.csr import CSRStorage, CSRStatus
|
||||
from litex.soc.interconnect.wishbone import Interface, SRAM, Decoder
|
||||
from litex.gen import LiteXModule
|
||||
from region import *
|
||||
|
||||
class PreemptiveInterface(LiteXModule):
|
||||
""" A preemptive interface is a manually controlled Wishbone interface
|
||||
that stands between multiple masters (potentially interconnects) and a
|
||||
single slave. A master controls which master (or interconnect) has access
|
||||
to the slave. This is to avoid bus contention by having multiple buses. """
|
||||
|
||||
def __init__(self, masters_len, slave):
|
||||
"""
|
||||
:param masters_len: The amount of buses accessing this slave. This number
|
||||
must be greater than one.
|
||||
:param slave: The slave device. This object must have an Interface object
|
||||
accessable as ``bus``.
|
||||
"""
|
||||
|
||||
assert masters_len > 1
|
||||
self.buses = []
|
||||
self.master_select = CSRStorage(masters_len, name='master_select', description='RW bitstring of which master interconnect to connect to')
|
||||
self.slave = slave
|
||||
|
||||
for i in range(masters_len):
|
||||
# Add the slave interface each master interconnect sees.
|
||||
self.buses.append(Interface(data_width=32, address_width=32, addressing="byte"))
|
||||
|
||||
"""
|
||||
Construct a combinatorial case statement. In verilog, the case
|
||||
statment would look like
|
||||
|
||||
always @ (*) case (master_select)
|
||||
1: begin
|
||||
// Assign slave to master 1,
|
||||
// Assign all other masters to dummy ports
|
||||
end
|
||||
2: begin
|
||||
// Assign slave to master 2,
|
||||
// Assign all other masters to dummy ports
|
||||
end
|
||||
// more cases:
|
||||
default: begin
|
||||
// assign slave to master 0
|
||||
// Assign all other masters to dummy ports
|
||||
end
|
||||
|
||||
Case statement is a dictionary, where each key is either the
|
||||
number to match or "default", which is the default case.
|
||||
|
||||
Avoiding latches:
|
||||
Left hand sign (assignment) is always an input.
|
||||
"""
|
||||
|
||||
def assign_for_case(current_case):
|
||||
asn = [ ]
|
||||
|
||||
for j in range(masters_len):
|
||||
if current_case == j:
|
||||
""" Assign all inputs (for example, slave reads addr
|
||||
from master) to outputs. """
|
||||
asn += [
|
||||
self.slave.bus.adr.eq(self.buses[j].adr),
|
||||
self.slave.bus.dat_w.eq(self.buses[j].dat_w),
|
||||
self.slave.bus.cyc.eq(self.buses[j].cyc),
|
||||
self.slave.bus.stb.eq(self.buses[j].stb),
|
||||
self.slave.bus.we.eq(self.buses[j].we),
|
||||
self.slave.bus.sel.eq(self.buses[j].sel),
|
||||
self.buses[j].dat_r.eq(self.slave.bus.dat_r),
|
||||
self.buses[j].ack.eq(self.slave.bus.ack),
|
||||
]
|
||||
else:
|
||||
""" Master bus will always read 0 when they are not
|
||||
selected, and writes are ignored. They will still
|
||||
get a response to avoid timeouts. """
|
||||
asn += [
|
||||
self.buses[j].dat_r.eq(0),
|
||||
self.buses[j].ack.eq(self.buses[j].cyc & self.buses[j].stb),
|
||||
]
|
||||
return asn
|
||||
|
||||
cases = {"default": assign_for_case(0)}
|
||||
for i in range(1, masters_len):
|
||||
cases[i] = assign_for_case(i)
|
||||
|
||||
self.comb += Case(self.master_select.storage, cases)
|
||||
|
||||
#TODO: Generalize CSR stuff
|
||||
class ControlLoopParameters(LiteXModule):
|
||||
""" Interface for the Linux CPU to write parameters to the CPU
|
||||
and for the CPU to write data back to the CPU without complex
|
||||
locking mechanisms.
|
||||
|
||||
This is a hack and will be replaced later with a more general
|
||||
memory region.
|
||||
"""
|
||||
def __init__(self):
|
||||
self.cl_I = CSRStorage(32, description='Integral parameter')
|
||||
self.cl_P = CSRStorage(32, description='Proportional parameter')
|
||||
self.deltaT = CSRStorage(32, description='Wait parameter')
|
||||
self.setpt = CSRStorage(32, description='Setpoint')
|
||||
self.zset = CSRStatus(32, description='Set Z position')
|
||||
self.zpos = CSRStatus(32, description='Measured Z position')
|
||||
|
||||
self.bus = Interface(data_width = 32, address_width = 32, addressing="word")
|
||||
self.width = 0x20
|
||||
self.sync += [
|
||||
If(self.bus.cyc == 1 and self.bus.stb == 1 and self.bus.ack == 0,
|
||||
Case(self.bus.adr[0:4], {
|
||||
0x0: self.bus.dat_r.eq(self.cl_I.storage),
|
||||
0x4: self.bus.dat_r.eq(self.cl_P.storage),
|
||||
0x8: self.bus.dat_r.eq(self.deltaT.storage),
|
||||
0xC: self.bus.dat_r.eq(self.setpt.storage),
|
||||
0x10: If(self.bus.we,
|
||||
self.zset.status.eq(self.bus.dat_w)
|
||||
).Else(
|
||||
self.bus.dat_r.eq(self.zset.status)
|
||||
),
|
||||
0x14: If(self.bus.we,
|
||||
self.zpos.status.eq(self.bus.dat_w),
|
||||
).Else(
|
||||
self.bus.dat_r.eq(self.zpos.status)
|
||||
),
|
||||
"default": self.bus.dat_r.eq(0xdeadbeef),
|
||||
}),
|
||||
self.bus.ack.eq(1),
|
||||
).Else(
|
||||
self.bus.ack.eq(0),
|
||||
)
|
||||
]
|
||||
|
||||
class PicoRV32(LiteXModule, MemoryMap):
|
||||
def add_params(self, origin):
|
||||
params = ControlLoopParameters()
|
||||
self.add_module("params", params)
|
||||
self.add_region('params', BasicRegion(origin, params.width, params.bus))
|
||||
|
||||
def __init__(self, name, start_addr=0x10000, irq_addr=0x10010):
|
||||
MemoryMap.__init__(self)
|
||||
self.name = name
|
||||
|
||||
self.masterbus = Interface(data_width=32, address_width=32, addressing="byte")
|
||||
|
||||
self.resetpin = CSRStorage(1, name="enable", description="PicoRV32 enable")
|
||||
|
||||
self.trap = CSRStatus(8, name="trap", description="Trap condition")
|
||||
self.d_adr = CSRStatus(32)
|
||||
self.d_dat_w = CSRStatus(32)
|
||||
self.dbg_insn_addr = CSRStatus(32)
|
||||
self.dbg_insn_opcode = CSRStatus(32)
|
||||
|
||||
self.comb += [
|
||||
self.d_adr.status.eq(self.masterbus.adr),
|
||||
self.d_dat_w.status.eq(self.masterbus.dat_w),
|
||||
]
|
||||
|
||||
# NOTE: need to compile to these extact instructions
|
||||
self.specials += Instance("picorv32_wb",
|
||||
p_COMPRESSED_ISA = 1,
|
||||
p_ENABLE_MUL = 1,
|
||||
p_PROGADDR_RESET=start_addr,
|
||||
p_PROGADDR_IRQ =irq_addr,
|
||||
p_REGS_INIT_ZERO = 1,
|
||||
o_trap = self.trap.status,
|
||||
|
||||
i_wb_rst_i = ~self.resetpin.storage,
|
||||
i_wb_clk_i = ClockSignal(),
|
||||
o_wbm_adr_o = self.masterbus.adr,
|
||||
o_wbm_dat_o = self.masterbus.dat_w,
|
||||
i_wbm_dat_i = self.masterbus.dat_r,
|
||||
o_wbm_we_o = self.masterbus.we,
|
||||
o_wbm_sel_o = self.masterbus.sel,
|
||||
o_wbm_stb_o = self.masterbus.stb,
|
||||
i_wbm_ack_i = self.masterbus.ack,
|
||||
o_wbm_cyc_o = self.masterbus.cyc,
|
||||
|
||||
o_pcpi_valid = Signal(),
|
||||
o_pcpi_insn = Signal(32),
|
||||
o_pcpi_rs1 = Signal(32),
|
||||
o_pcpi_rs2 = Signal(32),
|
||||
i_pcpi_wr = 0,
|
||||
i_pcpi_wait = 0,
|
||||
i_pcpi_rd = 0,
|
||||
i_pcpi_ready = 0,
|
||||
|
||||
i_irq = 0,
|
||||
o_eoi = Signal(32),
|
||||
|
||||
o_trace_valid = Signal(),
|
||||
o_trace_data = Signal(36),
|
||||
o_debug_state = Signal(2),
|
||||
|
||||
o_dbg_insn_addr = self.dbg_insn_addr.status,
|
||||
o_dbg_insn_opcode = self.dbg_insn_opcode.status,
|
||||
)
|
||||
|
||||
def do_finalize(self):
|
||||
self.dump_mmap(self.name + ".json")
|
||||
self.submodules.decoder = self.bus_submodule(self.masterbus)
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright 2023-2024 (C) Peter McGoron
|
||||
#
|
||||
# This file is a part of Upsilon, a free and open source software project.
|
||||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
||||
def minbits(n):
|
||||
from math import log2, floor
|
||||
""" Return the amount of bits necessary to store n. """
|
||||
return floor(log2(n) + 1)
|
||||
|
||||
Loading…
Reference in New Issue