From 556db1f361e2aadd369eb8d811fab2db8a001e6e Mon Sep 17 00:00:00 2001
From: Shell-ac <113789606+Shell-ac@users.noreply.github.com>
Date: Mon, 30 Jan 2023 14:09:49 -0500
Subject: [PATCH] Add files via upload

Verilog signal propagation testbench for the intsat module
---
 firmware/rtl/control_loop/intsat_testbench.v | 78 ++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 firmware/rtl/control_loop/intsat_testbench.v

diff --git a/firmware/rtl/control_loop/intsat_testbench.v b/firmware/rtl/control_loop/intsat_testbench.v
new file mode 100644
index 0000000..2b4660d
--- /dev/null
+++ b/firmware/rtl/control_loop/intsat_testbench.v
@@ -0,0 +1,78 @@
+//testbench for intsat module
+//Timothy Burman, 2022
+
+module intsat_testbench
+#(
+
+	parameter IN_LEN = 64,
+	parameter LTRUNC = 32
+
+	
+)
+(
+	//Outputs
+	output signed [IN_LEN-LTRUNC-1:0] outp
+);
+
+
+
+reg signed [IN_LEN-1:0] inp;
+
+intsat testbench (inp, outp);
+
+initial
+begin
+
+	//intial values
+	inp = 64'd410000000;
+
+	#10;
+
+	inp = inp + 1;
+	#10;
+
+	inp = inp + 1;
+	#10;
+
+	inp = inp + 1;
+	#10;
+
+	inp = inp + 1;
+	#10;
+
+	inp = inp + 1;
+	#10;
+
+	inp = inp + 1;
+	#10;
+
+	inp = inp + 10000000;
+	#10;
+
+	inp = inp + 10000000;
+	#10;
+
+
+	inp = inp - 1000000;
+	#10;
+
+	inp = -64'd1000000000;
+
+	#10;
+
+	inp = inp - 400095;
+
+	#10;
+
+
+
+
+	$finish;
+
+
+end
+
+
+
+
+endmodule
\ No newline at end of file