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add debug clock

This commit is contained in:
Peter McGoron 2023-04-20 15:20:42 -04:00
parent 51d31b9129
commit 40fd1ab6fe
2 changed files with 16 additions and 1 deletions
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13
firmware/rtl/base/base.v.m4
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@ -247,6 +247,8 @@ m4_define(CL_DATA_WID, CL_CONSTS_WID)
output reg [CL_DATA_WID-1:0] cl_word_out,
input cl_start_cmd,
output reg cl_finish_cmd
,output reg test_clock
);
wire [ADC_NUM-1:0] adc_conv_L;
@ -261,6 +263,17 @@ m4_dac_switch(DAC_PORTS, 5);
m4_dac_switch(DAC_PORTS, 6);
m4_dac_switch(DAC_PORTS, 7);
reg [ADC_CYCLE_HALF_WAIT_SIZ-1:0] counter = 0;
always @ (posedge clk) begin
if (counter >= ADC_CYCLE_HALF_WAIT) begin
counter <= 0;
test_clock <= !test_clock;
end else begin
counter <= counter + 1;
end
end
/* 1st adc is Type 1 (18 bit) */
wire [ADC_PORTS_CONTROL_LOOP-1:0] adc_conv_L_port_0;

4
firmware/soc.py
View File

@ -25,7 +25,8 @@ io = [
("dac_sck", 0, Pins("D12 K16 C15 J15 V11 U13 F3 G2"), IOStandard("LVCMOS33")),
("adc_conv", 0, Pins("V15 T11 N15 U18 U11 R10 R16 U17"), IOStandard("LVCMOS33")),
("adc_sck", 0, Pins("U16 R12 M16 R17 V16 R11 N16 T18"), IOStandard("LVCMOS33")),
("adc_sdo", 0, Pins("P14 T14 V17 P17 M13 R13 N14 R18"), IOStandard("LVCMOS33"))
("adc_sdo", 0, Pins("P14 T14 V17 P17 M13 R13 N14 R18"), IOStandard("LVCMOS33")),
("test_clock", 0, Pins("P18"), IOStandard("LVCMOS33"))
]
# TODO: Generate widths based off of include files (m4 generated)
@ -127,6 +128,7 @@ class Base(Module, AutoCSR):
self.kwargs["o_adc_conv"] = platform.request("adc_conv")
self.kwargs["i_adc_sdo"] = platform.request("adc_sdo")
self.kwargs["o_adc_sck"] = platform.request("adc_sck")
self.kwargs["o_test_clock"] = platform.request("test_clock")
with open("csr_bitwidth.json", mode='w') as f:
import json