changes
This commit is contained in:
parent
7a341a9632
commit
45f815c5d3
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@ -1,40 +1,3 @@
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/*************** Precision **************
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* The control loop is designed around these values, but generally
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* does not hardcode them.
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*
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* Since α and P are precalculated outside of the loop, their
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* conversion to numbers the loop understands is done outside of
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* the loop and in the kernel.
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*
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* The 18-bit ADC is twos-compliment, -10.24V to 10.24V,
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* with 78μV per increment.
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* The 20-bit DAC is twos-compliment, -10V to 10V.
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*
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* The `P` constant has a minimum value of 1e-7 with a precision
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* of 1e-9, and a maxmimum value of 1.
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*
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* The `I` constant has a minimum value of 1e-4 with a precision
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* of 1e-6 and a maximum value of 100.
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*
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* Δt is cycles/100MHz. This makes Δt at least 10 ns, with a
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* maximum of 1 ms.
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*
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* Intermediate values are 48-bit fixed-point integers multiplied
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* by the step size of the ADC. The first 18 bits are the whole
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* number and sign bits. This means intermediate values correspond
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* exactly to values as understood by the ADC, with extra precision.
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*
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* To get the normal fixed-point value of an intermediate value,
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* multiply it by 78e-6. To convert a normal fixed-point integer
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* to an intermediate value, multiply it by 1/78e-6. In both
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* cases, the conversion constant is a normal fixed-point integer.
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*
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* For instance, to encode the value 78e-6 as an intermediate
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* value, multiply it by 1/78e-6 to obtain 1. Thus the value
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* should be stored as 1 (whole bit) followed by zeros (fractional
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* bits).
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*/
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`include control_loop_cmds.vh
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`define ERR_WID (ADC_WID + 1)
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@ -58,7 +21,7 @@ module control_loop
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parameter ERR_WID_SIZ = 6,
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parameter DATA_WID = CONSTS_WID,
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parameter READ_DAC_DELAY = 5,
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parameter CYCLE_COUNT_WID = 16
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parameter CYCLE_COUNT_WID = 18
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) (
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input clk,
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@ -99,7 +62,6 @@ reg signed [CONSTS_WID-1:0] cl_p_reg_buffer = 0;
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reg [DELAY_WID-1:0] dely = 0;
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reg [DELAY_WID-1:0] dely_buffer = 0;
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reg running = 0;
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reg signed[DAC_DATA_WID-1:0] stored_dac_val = 0;
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@ -154,7 +116,13 @@ reg [STATESIZ-1:0] state = INIT_READ_FROM_DAC;
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* Measured value: ADC_WID.0
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* Setpoint: ADC_WID.0
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* - ----------------------------|
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* e: ERR_WID.0
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* e_unsc: ERR_WID.0
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* x 78e-6: 0.CONSTS_FRAC
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* - ----------------------------|
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* e_uncropped: ERR_WID.CONSTS_FRAC
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* -------------------------------------
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* e: CONSTS_WID.CONSTS_FRAC
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*
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*
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* α: CONSTS_WHOLE.CONSTS_FRAC | P: CONSTS_WHOLE.CONSTS_FRAC
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* e: ERR_WID.0 | e_p: ERR_WID.0
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@ -170,7 +138,34 @@ reg [STATESIZ-1:0] state = INIT_READ_FROM_DAC;
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*/
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/**** Calculate Error ****/
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wire [ERR_WID-1:0] err_cur = measured_value - setpoint;
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wire [ERR_WID-1:0] e_unsc = measured_value - setpoint;
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/**** convert error value to real value ****/
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wire [ERR_WID+CONSTS_FRAC-1:0] e_uncrop;
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reg mul_scale_err_fin = 0;
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boothmul #(
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.A1_LEN(ERR_WID),
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.A2_LEN(CONSTS_FRAC)
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) mul_scale_err (
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.clk(clk),
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.arm(arm_err_scale),
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.a1(e_unsc),
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.a2(adc_int_to_real),
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.outn(e_uncrop),
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.fin(mul_scale_err_fin)
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);
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wire [CONSTS_WID-1:0] e;
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intsat #(
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.A1_LEN(ERR_WID + CONSTS_FRAC),
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.A2_LEN(CONSTS_WID)
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) mul_scale_err_crop (
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.inp(e_uncrop),
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.outp(e)
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);
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/****** Multiplication *******
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* Truncation of a fixed-point integer to a smaller buffer requires
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@ -1,3 +1,4 @@
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`undefineall
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/*************** Precision **************
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* The control loop is designed around these values, but generally
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* does not hardcode them.
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@ -23,102 +24,48 @@
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* This is 127 to -128, with a resolution of 9.095e-13.
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*/
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/* If this design needs to be faster, you can:
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1) Pipeline the design
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2) Use DSPs
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With symbiflow + yosys there is no way to explicitly instantiate
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a DSP40 module. YOSYS may infer it but that might be unreliable.
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*/
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module control_loop_math #(
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parameter CONSTS_WHOLE = 8,
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parameter CONSTS_FRAC = 40,
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`define CONSTS_WID (CONSTS_WHOLE + CONSTS_FRAC)
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/* This number is the conversion from ADC voltage units to
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* a fixed-point number.
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* A micro-optimization could roll the ADC reading and the multiplier
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* together.
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* The LSB of this number is 2**(-CONSTS_FRAC).
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*/
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parameter INT_TO_REAL_WID = 27,
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parameter [INT_TO_REAL_WID-1:0] INT_TO_REAL = 'b101000111001001111101110010,
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/* This number is 1/(clock cycle).
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The number is interpreted so the least significant bit
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coincides with the LSB of a constant. */
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parameter SEC_PER_CYCLE_WID = 14,
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parameter [SEC_PER_CYCLE_WID-1:0] SEC_PER_CYCLE = 'b10101011110011,
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parameter DELAY_WID = 16,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 18,
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`define E_WID (ADC_WID + 1)
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/* How large the intermediate value should be. This should hold the ADC
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* value /as an integer/ along with the P, I values.
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* The OUT_FRAC value should usually but not always be the same as CONSTS_FRAC.
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*/
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parameter OUT_WHOLE = 20,
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parameter OUT_FRAC = 40,
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`define OUT_WID (OUT_WHOLE + OUT_FRAC)
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parameter CYCLE_COUNT_WID = 18
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) (
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input clk,
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input arm,
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output finished,
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output reg finished,
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input [ADC_WID-1:0] setpt,
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input [ADC_WID-1:0] measured,
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input [`CONSTS_WID-1:0] cl_P,
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input [`CONSTS_WID-1:0] cl_I,
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input [`CONSTS_WID-1:0] e_prev,
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input [CYCLE_COUNT_WID-1:0] cycles,
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input [DELAY_WID-1:0] dely,
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input [`ERR_WID-1:0] e_prev,
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input [`OUT_WID-1:0] adjval_prev,
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output reg [`CONSTS_WID-1:0] e_cur,
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output reg [DAC_DATA_WID-1:0] adjval
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output reg [`ERR_WID-1:0] e_cur,
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output [`OUT_WID-1:0] adj_val
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);
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/**** Stage 1: Convert error to real value, calculate Δt = cycles/100MHz
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*
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* e_unscaled: ERR_WID.0
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* x INT_TO_REAL: 0.INT_TO_REAL_WID
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*- -----------------------------
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* e_scaled_unsat: ERR_WID + INT_TO_REAL_WID
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*/
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/* Calculate current error */
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assign e_cur = setpt - measured;
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`define ERR_WID (ADC_WID + 1)
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wire [`ERR_WID-1:0] e_unscaled = setpt - measured;
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reg arm_stage_1 = 0;
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wire mul_scale_err_fin;
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`define E_UNTRUNC_WID (`ERR_WID + INT_TO_REAL_WID)
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wire [`E_UNTRUNC_WID-1:0] e_scaled_unsat;
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boothmul #(
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.A1_LEN(INT_TO_REAL_WID),
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.A2_LEN(`ERR_WID)
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) mul_scale_err (
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.clk(clk),
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.arm(arm_stage_1),
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.a1(INT_TO_REAL),
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.a2(e_unscaled),
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.outn(e_scaled_unsat),
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.fin(mul_scale_err_fin)
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);
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`define E_WID (`E_UNTRUNC_WID > `CONSTS_WID ? `CONSTS_WID : `E_UNTRUNC_WID)
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wire [`E_WID-1:0] e;
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`define E_FRAC (`E_WID < `CONSTS_FRAC ? `E_WID : `E_WID - `CONSTS_FRAC)
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`define E_WHOLE (`E_WID - `E_FRAC)
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/* Don't bother keeping numbers larger than the constant width
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* since the value will always fit in it. */
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generate if (`E_UNTRUNC_WID > `CONSTS_WID) begin
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intsat #(
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.IN_LEN(`E_UNTRUNC_WID),
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.LTRUNC(`E_UNTRUNC_WID - `CONSTS_WHOLE)
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) sat_mul_scale_err (
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.inp(e_scaled_unsat),
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.outp(e)
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);
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end else begin
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assign e = e_scaled_unsat;
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end endgenerate
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/* cycles: CYCLE_COUNT_WID.0
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/**** Stage 1: calculate Δt = cycles/100MHz
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* cycles: CYCLE_COUNT_WID.0
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* SEC_PER_CYCLE: 0....SEC_PER_CYCLE_WID
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* -x--------------------------------
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* dt_unsat: CYCLE_COUNT_WID + SEC_PER_CYCLE_WID
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@ -126,9 +73,12 @@ end endgenerate
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* Optimization note: the total width can be capped to below 1.
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*/
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reg arm_stage_1 = 0;
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`define DT_UNSAT_WID (CYCLE_COUNT_WID + SEC_PER_CYCLE_WID)
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wire [`DT_UNSAT_WID-1:0] dt_unsat;
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wire mul_dt_fin;
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boothmul #(
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.A1_LEN(CYCLE_COUNT_WID),
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.A2_LEN(SEC_PER_CYCLE_WID)
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@ -145,7 +95,7 @@ boothmul #(
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wire [`DT_WID-1:0] dt;
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`define DT_WHOLE (`DT_WID < `CONSTS_FRAC ? 0 : `CONSTS_FRAC - `DT_WID)
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`define DT_FRAC(`DT_WID - `DT_WHOLE)
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`define DT_FRAC (`DT_WID - `DT_WHOLE)
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generate if (`DT_UNSAT_WID > `CONSTS_WID) begin
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intsat #(
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@ -176,11 +126,12 @@ reg arm_stage2 = 0;
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wire [`CONSTS_WID-1:0] idt;
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mul_const #(
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/* TODO: does this autoinfer CONSTS_WID? */
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.CONSTS_WHOLE(CONSTS_WHOLE),
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.CONSTS_FRAC(CONSTS_FRAC),
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.IN_WHOLE(`DT_WHOLE),
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.IN_FRAC(`DT_FRAC)
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.IN_FRAC(`DT_FRAC),
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.OUT_WHOLE(CONSTS_WHOLE),
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.OUT_FRAC(CONSTS_FRAC)
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) mul_const_idt (
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.clk(clk),
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.inp(dt),
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@ -190,7 +141,7 @@ mul_const #(
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.finished(stage2_finished)
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);
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wire [`CONSTS_WID:0] pidt_untrunc = cl_P + idt;
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reg [`CONSTS_WID:0] pidt_untrunc;
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/* Assuming that the constraints on cl_P, I, and dt hold */
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wire [`CONSTS_WID-1:0] pidt = pidt_untrunc[`CONSTS_WID-1:0];
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@ -201,36 +152,51 @@ reg arm_stage3 = 0;
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wire epidt_finished;
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wire pe_finished;
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wire [`CONSTS_WID-1:0] epidt;
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wire [`OUT_WID-1:0] epidt;
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mul_const #(
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.CONSTS_WHOLE(`CONSTS_WHOLE),
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.CONSTS_FRAC(`CONSTS_FRAC),
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.IN_WHOLE(`E_WHOLE),
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.IN_FRAC(`E_FRAC)
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.IN_WHOLE(`E_WID),
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.IN_FRAC(0),
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.OUT_WHOLE(OUT_WHOLE),
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.OUT_FRAC(OUT_FRAC)
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) mul_const_epidt (
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.clk(clk),
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.inp(e),
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.inp(e_cur),
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.const_in(idt),
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.arm(arm_stage3),
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.outp(epidt),
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.finished(epidt_finished)
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);
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wire [`CONSTS_WID-1:0] pe;
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wire [`OUT_WID-1:0] pe;
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mul_const #(
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.CONSTS_WHOLE(`CONSTS_WHOLE),
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.CONSTS_FRAC(`CONSTS_FRAC),
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.IN_WHOLE(`E_WHOLE),
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.IN_FRAC(`E_FRAC)
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.IN_WHOLE(`ERR_WID),
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.IN_FRAC(0),
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.OUT_WHOLE(OUT_WHOLE),
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.OUT_FRAC(OUT_FRAC)
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) mul_const_pe (
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.clk(clk),
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.inp(e),
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.inp(e_prev),
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.const_in(idt),
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.arm(arm_stage3),
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.outp(pe),
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.finished(epidt_finished)
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);
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reg [`OUT_WID+1:0] adj_val_utrunc;
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/* = prev_adj + epidt - pe; */
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intsat #(
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.IN_LEN(`OUT_WID + 2),
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.LTRUNC(2)
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) adj_val_sat (
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.inp(adj_val_utrunc),
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.outp(adj_val)
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);
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/******* State machine ********/
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localparam WAIT_ON_ARM = 0;
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localparam WAIT_ON_STAGE_1 = 1;
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@ -258,6 +224,7 @@ always @ (posedge clk) begin
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end
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WAIT_ON_STAGE_2: begin
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if (stage2_finished) begin
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pidt_untrunc <= cl_P + idt;
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arm_stage_2 <= 0;
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arm_stage_3 <= 1;
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state <= WAIT_ON_STAGE_3;
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@ -265,6 +232,7 @@ always @ (posedge clk) begin
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end
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WAIT_ON_STAGE_3: begin
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if (epidt_finished && pe_finished) begin
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adj_val_utrunc <= prev_adj + epidt - pe;
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arm_stage3 <= 0;
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finished <= 1;
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state <= WAIT_ON_DISARM;
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|
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@ -157,17 +157,23 @@ static int64_t I_const, dt_const, P_const, setpt;
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static unsigned long seed, ;
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static void usage(char *argv0, int code) {
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std::cout << argv0 << " -I I -t dt -d delay -s seed -S setpt -P p [+verilator...]" << std::endl;
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std::cout << argv0 << " -d deviation -m mean -I I -t dt -d delay -s seed -S setpt -P p [+verilator...]" << std::endl;
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exit(code);
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}
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static void parse_args(int argc, char *argv[]) {
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const char *optstring = "I:t:s:P:h";
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const char *optstring = "I:t:s:P:d:m:h";
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int opt;
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Verilated::commandArgs(argc, argv);
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while ((opt = getopt(argc, argv, optstring)) != -1) {
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switch (opt) {
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case 'm':
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noise_mean = strtod(optstring, NULL);
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break;
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case 'd':
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dev_mean = strtod(optstring, NULL);
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break;
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case 'I':
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I_const = signed_to_fxp(optarg);
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break;
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@ -203,9 +209,4 @@ int main(int argc, char **argv) {
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mod = new Vtop;
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mod->clk = 0;
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mod->arm = 1;
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mod->setpt = setpt;
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mod->alpha = I_const * dt_const + P_const;
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mod->cl_p = P_const;
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mod->dy = 5;
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}
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|
|
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@ -1,27 +1,70 @@
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`include control_loop_cmds.vh
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module top
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#(
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parameter ADC_WID = 18,
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parameter DAC_WID = 24,
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parameter ADC_WID_LEN = 5,
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parameter ADC_POLARITY = 1,
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parameter ADC_PHASE = 0,
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parameter ADC_CYCLE_HALF_WAIT = 5,
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parameter ADC_TIMER_LEN = 3,
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parameter DAC_POLARITY = 0,
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parameter DAC_PHASE = 1,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID = 24,
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parameter DAC_WID_LEN = 5,
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parameter DAC_CYCLE_HALF_WAIT = 10,
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parameter DAC_TIMER_LEN = 4,
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parameter CONSTS_WID = 48,
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parameter DELAY_WID = 16
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)(
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input clk,
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input arm,
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input signed [ADC_WID-1:0] measured_data,
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output signed [DAC_WID-1:0] output_data,
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input signed [ADC_WID-1:0] setpt,
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input signed [CONSTS_WID-1:0] alpha,
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input signed [CONSTS_WID-1:0] cl_p,
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input [DELAY_WID-1:0] dy,
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input [DAC_DATA_WID-1:0] dac_in,
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output [DAC_DATA_WID-1:0] dac_out,
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output dac_input_ready,
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||||
|
||||
output signed [ADC_WID:0] err,
|
||||
output signed [CONSTS_WID-1:0] adj
|
||||
input [CONSTS_WID-1:0] word_into_loop,
|
||||
output [CONSTS_WID-1:0] word_outof_loop,
|
||||
input start_cmd,
|
||||
output finish_cmd,
|
||||
input [CONTROL_LOOP_CMD_WIDTH-1:0] cmd
|
||||
);
|
||||
|
||||
wire dac_miso;
|
||||
wire dac_mosi;
|
||||
wire dac_sck;
|
||||
wire ss_L;
|
||||
|
||||
spi_slave #(
|
||||
.WID(DAC_WID),
|
||||
.WID_LEN(DAC_WID_LEN),
|
||||
.POLARITY(DAC_POLARITY),
|
||||
.PHASE(DAC_PHASE)
|
||||
) dac_slave (
|
||||
.clk(clk),
|
||||
.sck(dac_sck),
|
||||
.mosi(dac_mosi),
|
||||
.miso(dac_miso),
|
||||
);
|
||||
|
||||
spi_master #(
|
||||
.WID(DAC_WID),
|
||||
.WID_LEN(DAC_WID_LEN),
|
||||
.POLARITY(DAC_POLARITY),
|
||||
.PHASE(DAC_PHASE),
|
||||
.CYCLE_HALF_WAIT(DAC_CYCLE_HALF_WAIT),
|
||||
.TIMER_LEN(DAC_TIMER_LEN)
|
||||
) dac_master (
|
||||
.clk(clk),
|
||||
.from_slave(dac_set_data),
|
||||
.miso(dac_miso),
|
||||
.to_slave(
|
||||
.mosi(dac_mosi),
|
||||
|
||||
wire adc_sck;
|
||||
wire adc_ss;
|
||||
wire adc_miso;
|
||||
|
|
@ -80,23 +123,7 @@ control_loop #(
|
|||
.DAC_PHASE(DAC_PHASE)
|
||||
) cloop (
|
||||
.clk(clk),
|
||||
.arm(arm),
|
||||
|
||||
.adc_sck(adc_sck),
|
||||
.adc_in(adc_miso),
|
||||
.adc_conv(adc_ss),
|
||||
|
||||
.dac_sck(dac_sck),
|
||||
.dac_ss(dac_ss),
|
||||
.dac_out(dac_mosi),
|
||||
|
||||
.setpt_in(setpt),
|
||||
.cl_alpha_in(alpha),
|
||||
.cl_p_in(cl),
|
||||
.delay_in(dy),
|
||||
|
||||
.err(err_cur),
|
||||
.adj(adj)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -62,3 +62,12 @@ same for fixed point binary and regular decimals.
|
|||
Addition: W1.F1 + W2.F2 = [max(W1,W2)+1].[max(F1,F2)]
|
||||
|
||||
Multiplication: W1.F1W2.F2 = [W1+W2].[F1+F2]
|
||||
|
||||
|
||||
When multiplying two fixed point integers, where the decimal points
|
||||
do not correspond to the same points, then:
|
||||
|
||||
* the output has the same number of bits as a normal addition/multiplication
|
||||
* for multiplication, the LSB is interpreted as position `m+n`, where
|
||||
`m` is the interpretation of the LSB of the first integer and `n` as
|
||||
the LSB of the second.
|
||||
|
|
|
|||
|
|
@ -1,26 +1,29 @@
|
|||
module mul_const #(
|
||||
parameter CONSTS_WHOLE = 8,
|
||||
parameter CONSTS_FRAC = 40,
|
||||
parameter CONSTS_WID = CONSTS_WHOLE + CONSTS_FRAC,
|
||||
`define CONSTS_WID (CONSTS_WHOLE + CONSTS_FRAC)
|
||||
parameter IN_WHOLE = CONSTS_WHOLE,
|
||||
parameter IN_FRAC = CONSTS_FRAC,
|
||||
parameter IN_WID = IN_WHOLE + IN_FRAC
|
||||
`define IN_WID (IN_WHOLE + IN_FRAC)
|
||||
parameter OUT_WHOLE = 20,
|
||||
parameter OUT_FRAC = 40
|
||||
`define OUT_WID (OUT_WHOLE + OUT_FRAC)
|
||||
) (
|
||||
input clk,
|
||||
input signed [IN_WID-1:0] inp,
|
||||
input signed [CONSTS_WID-1:0] const_in,
|
||||
input signed [`IN_WID-1:0] inp,
|
||||
input signed [`CONSTS_WID-1:0] const_in,
|
||||
input arm,
|
||||
|
||||
output signed [CONSTS_WID-1:0] outp,
|
||||
output signed [`OUT_WID-1:0] outp,
|
||||
output finished
|
||||
);
|
||||
|
||||
localparam UNSAT_WID = CONSTS_WID + IN_WID;
|
||||
wire signed [UNSAT_WID-1:0] unsat;
|
||||
`define UNSAT_WID (`CONSTS_WID + `IN_WID)
|
||||
wire signed [`UNSAT_WID-1:0] unsat;
|
||||
|
||||
boothmul #(
|
||||
.A1_LEN(CONSTS_WID),
|
||||
.A2_LEN(IN_WID)
|
||||
.A1_LEN(`CONSTS_WID),
|
||||
.A2_LEN(`IN_WID)
|
||||
) mul (
|
||||
.clk(clk),
|
||||
.arm(arm),
|
||||
|
|
@ -30,20 +33,26 @@ boothmul #(
|
|||
.fin(finished)
|
||||
);
|
||||
|
||||
localparam RIGHTTRUNC_WID = UNSAT_WID - IN_FRAC;
|
||||
wire signed [RIGHTTRUNC_WID-1:0] rtrunc =
|
||||
unsat[UNSAT_WID-1:IN_FRAC];
|
||||
`define RIGHTTRUNC_WID (CONSTS_WHOLE + IN_WHOLE + OUT_FRAC)
|
||||
`define UNSAT_FRAC (CONSTS_FRAC + IN_FRAC)
|
||||
wire signed [`RIGHTTRUNC_WID-1:0] rtrunc =
|
||||
unsat[`UNSAT_WID-1:(`UNSAT_FRAC - OUT_FRAC)];
|
||||
|
||||
generate if (IN_WHOLE > 0) begin
|
||||
generate if (OUT_WHOLE < CONSTS_WHOLE + IN_WHOLE) begin
|
||||
intsat #(
|
||||
.IN_LEN(RIGHTTRUNC_WID),
|
||||
.LTRUNC(IN_WHOLE)
|
||||
.IN_LEN(`RIGHTTRUNC_WID),
|
||||
.LTRUNC(CONSTS_WHOLE + IN_WHOLE - OUT_WHOLE)
|
||||
) sat (
|
||||
.inp(rtrunc),
|
||||
.outp(outp)
|
||||
);
|
||||
end else begin
|
||||
end else if (OUT_WHOLE == CONSTS_WHOLE + IN_WHOLE) begin
|
||||
assign outp = rtrunc;
|
||||
end else begin
|
||||
assign outp[`RIGHTTRUNC_WID-1:0] = rtrunc;
|
||||
assign outp[`OUT_WID-1:`RIGHTTRUNC_WID] = {
|
||||
(`OUT_WID-`RIGHTTRUNC_WID){rtrunc[`RIGHTTRUNC_WID-1]}
|
||||
};
|
||||
end endgenerate
|
||||
|
||||
`ifdef VERILATOR
|
||||
|
|
|
|||
|
|
@ -29,12 +29,15 @@ static void init(int argc, char **argv) {
|
|||
|
||||
static void satmul(int64_t const_in, int64_t inp) {
|
||||
int64_t r = const_in * inp;
|
||||
if (r >= BITMASK(48))
|
||||
if (r >= BITMASK(48)) {
|
||||
return BITMASK(48);
|
||||
else if (r <= -BITMASK(48))
|
||||
return -BITMASK(48);
|
||||
else
|
||||
} else if (r <= -BITMASK(48)) {
|
||||
V allzero = ~((V) 0);
|
||||
// make (siz - 1) zero bits
|
||||
return allzero & (allzero << (siz - 1));
|
||||
} else {
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
||||
#define RUNS 10000
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@ module sign_extend #(
|
|||
parameter WID1 = 18,
|
||||
parameter WID2 = 24
|
||||
) (
|
||||
input signed [WID1-1:0] b1,
|
||||
output signed [WID2-1:0] b2
|
||||
input [WID1-1:0] b1,
|
||||
output [WID2-1:0] b2
|
||||
);
|
||||
|
||||
assign b2[WID1-1:0] = b1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue