ram_shim: simulate
This commit is contained in:
parent
15480f11da
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4ba004336c
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@ -2,12 +2,28 @@
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.PHONY: test clean
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RAM_FIFO_SRC= ram_fifo.v ram_fifo_sim.cpp
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test: obj_dir/Vram_fifo
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@./obj_dir/Vram_fifo && echo 'Vram_fifo successful'
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obj_dir/Vram_fifo.mk:
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test: obj_dir/Vram_fifo obj_dir/Vram_shim
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RAM_FIFO_SRC= ram_fifo.v ram_fifo_dual_port.v ram_fifo_sim.cpp
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obj_dir/Vram_fifo.mk: ${RAM_FIFO_SRC}
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verilator --cc --exe -Wall --trace --trace-fst \
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${RAM_FIFO_SRC}
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obj_dir/Vram_fifo: obj_dir/Vram_fifo.mk
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cd obj_dir && make -f Vram_fifo.mk
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@./obj_dir/Vram_fifo && echo 'Vram_fifo successful'
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RAM_SHIM_SRC= ram_shim.v ram_fifo.v ram_fifo_dual_port.v ram_shim_sim.cpp
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obj_dir/Vram_shim.mk: ${RAM_SHIM_SRC} ram_shim_cmds.vh ram_shim_cmds.h
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verilator --cc --exe -Wall --trace --trace-fst \
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-DRAM_SHIM_DEBUG \
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${RAM_SHIM_SRC}
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obj_dir/Vram_shim: obj_dir/Vram_shim.mk ram_shim_sim.cpp
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cd obj_dir && make -f Vram_shim.mk
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@./obj_dir/Vram_shim && echo 'Vram_shim successful'
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####### Codegen ########
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ram_shim_cmds.h: ram_shim_cmds.vh
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echo '#pragma once' > ram_shim_cmds.h
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sed 's/`define/#define/g; s/`//g' ram_shim_cmds.vh >> ram_shim_cmds.h
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@ -1,3 +1,7 @@
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/* Implements a synchronous(!) FIFO using inferred Block RAM. This
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* must wrap "ram_fifo_dual_port" due to difficulties YOSYS has with
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* inferring Block RAM: refer to that module for details.
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*/
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module ram_fifo #(
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parameter DAT_WID = 24,
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parameter FIFO_DEPTH_WID = 11,
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@ -1,88 +1,184 @@
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/* Ram shim. This is an interface designed for a LiteX RAM
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* DMA module. It can also be connected to a simulator.
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/* Ram shim. This is an interface designed for a LiteX RAM DMA module.
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* It can also be connected to a simulator.
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*
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* The read end is implemented in C since all of this is
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* backed by memory.
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* The read end is implemented in C since all of this is backed by memory.
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*
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* In between the system RAM and the raster scan is a block RAM FIFO so
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* scanning is not interrupted by transient RAM accesses from the system.
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*
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* THIS MODULE ASSUMES that RAM_WORD < DAT_WID < RAM_WORD*2.
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*
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* TODO: Buffer the data (using something like block ram) and
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* write it out asynchronously. This will require instantiating
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* the block ram primitive directly for Yosys. This should make
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* writes to RAM smoother, and reads smoother when the CPU is
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* reading the data.
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*/
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`include "ram_shim_cmds.vh"
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module ram_shim #(
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parameter BASE_ADDR = 32'h1000000,
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parameter MAX_BYTE_WID = 13,
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parameter DAT_WID = 24,
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parameter RAM_WORD = 16,
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parameter RAM_WID = 32
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) (
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input clk,
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input signed [DAT_WID-1:0] data,
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input commit,
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input rst,
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/* Raster control interface. The kernel allocates memory and informs the
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* shim what the memory location is, and how long it is (max certain length).
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* This is also where the current write pointer is found so that the
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* kernel can read data from the scanner into memory and out to the
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* controlling computer. */
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input [RAM_WID-1:0] cmd_data,
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input [`RAM_SHIM_CMD_WID-1:0] cmd,
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input cmd_active,
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output reg cmd_finished,
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output [RAM_WID-1:0] cmd_data_out,
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input [DAT_WID-1:0] data,
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input data_commit,
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output reg finished,
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/* Used by the kernel code to request the current
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* location of the FIFO head. Used to memcpy data,
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* it might better than repeatedly calling a FIFO
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* read.
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*/
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input read_end_req_off,
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output reg [RAM_WID-1:0] read_end_addr,
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output reg read_end_req_valid,
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`ifdef RAM_SHIM_DEBUG
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wire fifo_steady,
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`endif
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/* RAM DMA interface. */
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output reg [RAM_WORD-1:0] word,
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output [RAM_WID-1:0] addr,
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output reg write,
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input valid
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);
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localparam WAIT_ON_COMMIT = 0;
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localparam HIGH_WORD_LOAD = 1;
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localparam WAIT_ON_HIGH_WORD = 2;
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localparam WAIT_ON_COMMIT_DEASSERT = 3;
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reg [2:0] state = WAIT_ON_COMMIT;
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/* Control interface code.
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* Each of these are BYTE level addresses. Most numbers in Verilog are
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* BITS. When converting from bits to bytes, divide by 8. */
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reg [MAX_BYTE_WID-1:0] offset = 0;
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assign addr = BASE_ADDR + {{(RAM_WID - MAX_BYTE_WID){1'b0}}, offset};
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initial read_end_req_valid = 0;
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reg [RAM_WID-1:0] loc_start = 0;
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reg [RAM_WID-1:0] loc_len = 0;
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reg [RAM_WID-1:0] loc_off = 0;
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assign addr = loc_start + loc_off;
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always @ (posedge clk) begin
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if (read_end_req_off && !read_end_req_valid) begin
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read_end_req_valid = 1;
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read_end_addr <= addr;
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end else if (read_end_req_valid && !read_end_req_off) begin
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read_end_req_valid <= 0;
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if (cmd_active && !cmd_finished) case (cmd)
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`RAM_SHIM_WRITE_LOC: begin
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loc_start <= cmd_data;
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loc_off <= 0;
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cmd_finished <= 1;
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end
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`RAM_SHIM_WRITE_LEN: begin
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loc_len <= cmd_data;
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loc_off <= 0;
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cmd_finished <= 1;
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end
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`RAM_SHIM_READ_PTR: begin
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cmd_data_out <= addr;
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cmd_finished <= 1;
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end
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endcase else begin
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cmd_finished <= 0;
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end
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end
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/* Block RAM FIFO controller. */
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reg read_enable = 0;
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reg write_enable = 0;
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reg [DAT_WID-1:0] write_dat = 0;
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wire [DAT_WID-1:0] read_dat;
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wire empty;
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wire full;
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ram_fifo #(
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.DAT_WID(DAT_WID)
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) pre_fifo (
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.clk(clk),
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.rst(rst),
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.read_enable(read_enable),
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.write_enable(write_enable),
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.write_dat(write_dat),
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.read_dat(read_dat),
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.empty(empty),
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.full(full)
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);
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/* Code to take data from Block RAM and put it into System RAM. */
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localparam WAIT_ON_EMPTY = 0;
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localparam READ_OFF_FIFO = 1;
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localparam HIGH_WORD_LOAD = 2;
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localparam WAIT_ON_HIGH_WORD = 3;
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reg [1:0] writestate = WAIT_ON_EMPTY;
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/* Originally the simulation code checked if the intermediate FIFO was
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* empty, and then stopped running the simulation. This led to an off
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* by one error where the very last value pushed was not read. Instead,
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* the simulator now checks for steady-ness, which means that the always
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* block has idled at the WAIT_ON_EMPTY state for two cycles.
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*/
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`ifdef RAM_SHIM_DEBUG
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reg [1:0] prev_writestate;
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always @ (posedge clk) prev_writestate <= writestate;
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assign fifo_steady = prev_writestate == WAIT_ON_EMPTY && writestate == WAIT_ON_EMPTY;
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`endif
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always @ (posedge clk) begin
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case (state)
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WAIT_ON_COMMIT: if (commit) begin
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word <= data[RAM_WORD-1:0];
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case (writestate)
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WAIT_ON_EMPTY: if (!empty) begin
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writestate <= READ_OFF_FIFO;
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/* This value is raised on the at the beginning of the
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* next clock cycle. A read takes one clock cycle, so
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* the next clock cycle has to disarm read_enable, and
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* then the cycle *after that* must read the data from
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* the FIFO.
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*/
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read_enable <= 1;
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end
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READ_OFF_FIFO: if (read_enable) begin
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read_enable <= 0;
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end else begin
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word <= read_dat[RAM_WORD-1:0];
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write <= 1;
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state <= HIGH_WORD_LOAD;
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writestate <= HIGH_WORD_LOAD;
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end
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HIGH_WORD_LOAD: if (valid) begin
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offset <= offset + (RAM_WORD/2);
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if (loc_off == loc_len - 1)
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loc_off <= 0;
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else
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loc_off <= loc_off + RAM_WORD/8;
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write <= 0;
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word <= {{(RAM_WORD*2 - DAT_WID){data[DAT_WID-1]}},
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data[DAT_WID-1:RAM_WORD]};
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state <= WAIT_ON_HIGH_WORD;
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word <= {{(RAM_WORD*2 - DAT_WID){read_dat[DAT_WID-1]}},
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read_dat[DAT_WID-1:RAM_WORD]};
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writestate <= WAIT_ON_HIGH_WORD;
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end
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WAIT_ON_HIGH_WORD: if (!write) begin
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write <= 1;
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end else if (valid) begin
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offset <= offset + (RAM_WORD / 2);
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state <= WAIT_ON_COMMIT_DEASSERT;
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finished <= 1;
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end
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WAIT_ON_COMMIT_DEASSERT: if (!commit) begin
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finished <= 0;
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if (loc_off == loc_len - 1)
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loc_off <= 0;
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else
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loc_off <= loc_off + RAM_WORD/8;
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writestate <= WAIT_ON_EMPTY;
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write <= 0;
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end
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endcase
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end
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/* read to memory */
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always @ (posedge clk) begin
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if (data_commit && !write_enable && !full) begin
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write_dat <= data;
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write_enable <= 1;
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end else if (data_commit && write_enable) begin
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write_enable <= 0;
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finished <= 1;
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end else if (!data_commit && finished) begin
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finished <= 0;
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write_enable <= 0;
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end
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end
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/*
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`ifdef VERILATOR
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initial begin
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$dumpfile("ram_shim.vcd");
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$dumpvars;
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end
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`endif
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*/
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endmodule
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@ -0,0 +1,5 @@
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`define RAM_SHIM_NO_OP 0
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`define RAM_SHIM_WRITE_LOC 1
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`define RAM_SHIM_WRITE_LEN 2
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`define RAM_SHIM_READ_PTR 3
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`define RAM_SHIM_CMD_WID 8
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@ -0,0 +1,207 @@
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#include <memory>
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#include <cassert>
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#include <limits>
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#include <cstdint>
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#include <cstring>
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#include <cstdlib>
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#include <iostream>
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#include <random>
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#include <unistd.h>
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#include <verilated.h>
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#include "ram_shim_cmds.h"
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#include "Vram_shim.h"
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using ModType = Vram_shim;
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ModType *mod;
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uint32_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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static void run_clock() {
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for (int i = 0; i < 2; i++) {
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mod->clk = !mod->clk;
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mod->eval();
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main_time++;
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}
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}
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static void cleanup_exit() {
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mod->final();
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delete mod;
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}
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static void init(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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Verilated::traceEverOn(true);
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mod = new ModType;
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mod->clk = 0;
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atexit(cleanup_exit);
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char *seed = getenv("RANDOM_SEED");
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if (seed) {
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unsigned long i = strtoul(seed, NULL, 10);
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srand((unsigned int)i);
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}
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}
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static void init_values() {
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mod->rst = 0;
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mod->cmd_data = 0;
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mod->cmd = 0;
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mod->cmd_active = 0;
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mod->data = 0;
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mod->data_commit = 0;
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mod->valid = 0;
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}
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using V = uint32_t;
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// Verilator makes all ports unsigned, even when marked as signed in
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// Verilog.
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V sign_extend(V x, unsigned len) {
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// if high bit is 1
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if (x >> (len - 1) & 1) {
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// This mask selects all bits below the highest bit.
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// By inverting it, it selects the highest bit, and all
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// higher bits that must be sign extended.
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V mask = (1 << len) - 1;
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// Set all high bits to 1. The mask has all bits lower
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// than the highest bit 0, so the bits in "x" pass through.
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return ~mask | x;
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} else {
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return x;
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}
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}
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#define MASK_TO(x,n) ((x) & ((1 << (n)) - 1))
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/* Test memory buffering and memory interface.
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* The memory interface takes 16 bits integers at a time. The ram interface
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* runs slower than the insertion loop, to test buffering.
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*
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* The values given to the Verilog module are also stored in memory as
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* 32 bit integers. These are compared with the memory that simulates the
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* RAM interface.
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*/
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#define MEMORY_LEN 1000 // How many 32 bit integers
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#define MEMORY_LEN_16BIT MEMORY_LEN*2 // How many 16 bit parts
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#define MEMORY_START 0x10241024
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static std::array<uint16_t, MEMORY_LEN_16BIT> backing_memory;
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static std::array<bool, MEMORY_LEN_16BIT> backing_memory_accessed;
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#define MEMORY_WAIT_TIME 50
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static void handle_memory() {
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// Memory counter is used to simulate RAM delay.
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// TODO; random ram delay
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static uint32_t memory_counter = 0;
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if (mod->write) {
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if (memory_counter == MEMORY_WAIT_TIME) {
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mod->valid = 1;
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return;
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}
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if (memory_counter == 0) {
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uint32_t memory_access_ind = 0;
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assert(mod->addr >= MEMORY_START);
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memory_access_ind = mod->addr - MEMORY_START;
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// Addresses are bytes, but writes are always 16 bits.
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// Ensure we are writing to a 16 bit boundary.
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assert(memory_access_ind % 2 == 0);
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memory_access_ind /= 2;
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// Check to make sure that the RAM interface is not overwriting
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// memory locations. For now, it should not do that.
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assert(!backing_memory_accessed[memory_access_ind]);
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backing_memory_accessed[memory_access_ind] = true;
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assert(memory_access_ind < MEMORY_LEN_16BIT);
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backing_memory[memory_access_ind] = mod->word;
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// printf("RAM end: %x @ %d\n", backing_memory[memory_access_ind], memory_access_ind);
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}
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memory_counter++;
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} else {
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mod->valid = 0;
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assert(memory_counter == MEMORY_WAIT_TIME || memory_counter == 0);
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memory_counter = 0;
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}
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}
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static void init_memory() {
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mod->cmd_data = MEMORY_LEN;
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mod->cmd = RAM_SHIM_WRITE_LEN;
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mod->cmd_active = 1;
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while (!mod->cmd_finished)
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run_clock();
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mod->cmd_active = 0;
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run_clock();
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mod->cmd_data = MEMORY_START;
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mod->cmd = RAM_SHIM_WRITE_LOC;
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mod->cmd_active = 1;
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while (!mod->cmd_finished)
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run_clock();
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mod->cmd_active = 0;
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run_clock();
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}
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static std::array<uint32_t, MEMORY_LEN> generated_memory;
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constexpr int CYCLE_WAIT = 10;
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int main(int argc, char **argv) {
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init(argc, argv);
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init_values();
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init_memory();
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/* Every CYCLE_WAIT cycles, push one value to RAM.
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* This should be smaller than the amount of time it takes for
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* the ram to "process" the added value.
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*/
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int i = 0;
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int cntr = 0;
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while (i < MEMORY_LEN) {
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run_clock();
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handle_memory();
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if (cntr == CYCLE_WAIT) {
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if (!mod->finished && !mod->data_commit) {
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generated_memory[i] = sign_extend(MASK_TO(rand(), 24), 24);
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// printf("Sending: %d, %x\n", i, generated_memory[i]);
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mod->data = generated_memory[i];
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mod->data_commit = 1;
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} else if (mod->finished && mod->data_commit) {
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mod->data_commit = 0;
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i++;
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cntr = 0;
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}
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||||
} else {
|
||||
cntr++;
|
||||
}
|
||||
}
|
||||
|
||||
fprintf(stderr, "Waiting on bram\n");
|
||||
while (!mod->fifo_steady) {
|
||||
run_clock();
|
||||
handle_memory();
|
||||
}
|
||||
handle_memory();
|
||||
fprintf(stderr, "Bram complete\n");
|
||||
|
||||
for (i = 0; i < MEMORY_LEN_16BIT; i+=2) {
|
||||
uint32_t nv = (uint32_t)backing_memory[i+1] << 16 | backing_memory[i];
|
||||
if (generated_memory[i/2] != nv) {
|
||||
fprintf(stderr, "%d: %x != %x\n", i, generated_memory[i/2], nv);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue