add custom SoC generator
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# This file incorporates code from litex-boards.
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# BSD 2-Clause License
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#
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# Copyright (c) Copyright 2012-2022 Enjoy-Digital.
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# Copyright (c) Copyright 2012-2022 / LiteX-Hub community.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# There is nothing fundamental about the Arty A7(35|100)T to this
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# design, but another eval board will require some porting.
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from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# Refer to `A7-constraints.xdc` for pin names.
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# SS MOSI MISO SCK
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io = [
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("dac0", 0, Pins("G13 B11 A11 D12"), IOStandard("LVCMOS33")),
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("dac1", 0, Pins("D13 B18 A18 K16"), IOStandard("LVCMOS33")),
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("dac2", 0, Pins("E15 E16 D15 C15"), IOStandard("LVCMOS33")),
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("dac3", 0, Pins("J17 J18 K15 J15"), IOStandard("LVCMOS33")),
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("dac4", 0, Pins("U12 V12 V10 V11"), IOStandard("LVCMOS33")),
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("dac5", 0, Pins("U14 V14 T13 U13"), IOStandard("LVCMOS33")),
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("dac6", 0, Pins("D4 D3 F4 F3"), IOStandard("LVCMOS33")),
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("dac7", 0, Pins("E2 D2 H2 G2"), IOStandard("LVCMOS33")),
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("adc0", 0, Pins("V15 U16 P14"), IOStandard("LVCMOS33")),
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("adc1", 0, Pins("T11 R12 T14"), IOStandard("LVCMOS33")),
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("adc2", 0, Pins("T15 T16 N15"), IOStandard("LVCMOS33")),
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("adc3", 0, Pins("M16 V17 U18"), IOStandard("LVCMOS33")),
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("adc4", 0, Pins("U11 V16 M13"), IOStandard("LVCMOS33")),
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("adc5", 0, Pins("R10 R11 R13"), IOStandard("LVCMOS33")),
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("adc6", 0, Pins("R15 P15 R16"), IOStandard("LVCMOS33")),
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("adc7", 0, Pins("N16 N14 U17"), IOStandard("LVCMOS33"))
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]
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_dram:
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self.clock_domains.cd_sys4x = ClockDomain()
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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# PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(rst | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_eth, 25e6)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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# IdelayCtrl.
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if with_dram:
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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class CryoSNOM1SoC(SoCCore):
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def __init__(self, variant):
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sys_clk_freq = int(100e6)
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platform = board_spec.Platform(variant=variant, toolchain="symbiflow")
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self.submodules.crg = _CRG(platform, sys_clk_freq, True)
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# SoCCore does not have sane defaults (no integrated rom)
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SoCCore.__init__(self,
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clk_freq=sys_clk_freq,
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toolchain="symbiflow",
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platform = platform,
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bus_standard = "wishbone",
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ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr CryoSNOM1 0.1",
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bus_data_width = 32,
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bus_address_width = 32,
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bus_timeout = int(1e6),
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cpu_type = "vexriscv",
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integrated_rom_size=0x20000,
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integrated_sram_size = 0x2000,
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csr_data_width=32,
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csr_address_width=14,
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csr_paging=0x800,
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csr_ordering="big",
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timer_uptime = True)
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 8192
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)
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, dynamic_ip=True)
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# Add the DAC and ADC pins as GPIO. They will be used directly
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# by Zephyr.
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platform.add_extension(io)
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for name in [f"dac{n}" for n in range(0,8)]:
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setattr(self.submodules, name, GPIOTristate(platform.request(name)))
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for name in [f"adc{n}" for n in range(0,8)]:
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setattr(self.submodules, name, GPIOTristate(platform.request(name)))
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def main():
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soc = CryoSNOM1SoC("a7-35")
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builder = Builder(soc, csr_json="csr.json")
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builder.build()
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if __name__ == "__main__":
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main()
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