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move preprocessed generation to common makefile

This commit is contained in:
Peter McGoron 2023-03-16 16:32:03 +00:00
parent 23d29abdd7
commit 50ef091578
3 changed files with 2 additions and 4 deletions
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2
firmware/rtl/common.makefile
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@ -3,3 +3,5 @@
#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@ #m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
# NOTE: f4pga yosys does not support `line directives. Use above for debug. # NOTE: f4pga yosys does not support `line directives. Use above for debug.
m4 -P $< > $@ m4 -P $< > $@
%_preprocessed.v: %.v
verilator -P -E $< > $@

2
firmware/rtl/spi/Makefile
View File

@ -12,8 +12,6 @@ CODEGEN_FILES= spi_master_ss_preprocessed.v spi_master_preprocessed.v \
spi_master_ss_no_write_preprocessed.v spi_switch_preprocessed.v spi_master_ss_no_write_preprocessed.v spi_switch_preprocessed.v
codegen: ${CODEGEN_FILES} codegen: ${CODEGEN_FILES}
%_preprocessed.v: %.v
verilator -P -E $< > $@
SRC= spi_switch.v spi_switch_sim.cpp SRC= spi_switch.v spi_switch_sim.cpp
obj_dir/Vspi_switch.mk: $(SRC) obj_dir/Vspi_switch.mk: $(SRC)

2
firmware/rtl/waveform/Makefile
View File

@ -7,8 +7,6 @@ test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
CODEGEN_FILES=bram_interface_preprocessed.v waveform_preprocessed.v CODEGEN_FILES=bram_interface_preprocessed.v waveform_preprocessed.v
codegen: ${CODEGEN_FILES} codegen: ${CODEGEN_FILES}
%_preprocessed.v: %.v
verilator -P -E $< > $@
bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp