move preprocessed generation to common makefile

firmware/rtl/common.makefile

@@ -3,3 +3,5 @@
 	#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
 	# NOTE: f4pga yosys does not support `line directives. Use above for debug.
 	m4 -P $< > $@
+%_preprocessed.v: %.v
+	verilator -P -E $< > $@

firmware/rtl/spi/Makefile

@@ -12,8 +12,6 @@ CODEGEN_FILES= spi_master_ss_preprocessed.v spi_master_preprocessed.v \
                spi_master_ss_no_write_preprocessed.v spi_switch_preprocessed.v
 
 codegen: ${CODEGEN_FILES}
-%_preprocessed.v: %.v
-	verilator -P -E $< > $@
 
 SRC= spi_switch.v spi_switch_sim.cpp
 obj_dir/Vspi_switch.mk: $(SRC)

firmware/rtl/waveform/Makefile

@@ -7,8 +7,6 @@ test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
 CODEGEN_FILES=bram_interface_preprocessed.v waveform_preprocessed.v
 
 codegen: ${CODEGEN_FILES}
-%_preprocessed.v: %.v
-	verilator -P -E $< > $@
 
 bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp