From 540612e3059565dadd1a0aa807cb380ed7707740 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Fri, 21 Apr 2023 14:26:37 -0400 Subject: [PATCH] GUIDELINES.md --- GUIDELINES.md | 1 + 1 file changed, 1 insertion(+) diff --git a/GUIDELINES.md b/GUIDELINES.md index eff83fd..311c59a 100644 --- a/GUIDELINES.md +++ b/GUIDELINES.md @@ -29,6 +29,7 @@ See also [Dan Gisselquist][1]'s rules for FPGA development. takes care of connecting modules together and assigning each register a memory location. * Keep all Verilog as generic as possible. +* Always initialize registers. # Software