pass yosys

firmware/rtl/Makefile

@@ -1,4 +1,4 @@
-all: make_base make_control_loop make_waveform
+all: make_base make_spi make_control_loop make_waveform
 
 make_base:
 	cd base && make codegen
@@ -8,3 +8,8 @@ make_control_loop:
 	cd control_loop && make codegen
 make_waveform:
 	cd waveform && make codegen
+clean:
+	cd base && make clean
+	cd spi && make clean
+	cd control_loop && make clean
+	cd waveform && make clean

firmware/rtl/base/Makefile

@@ -5,3 +5,5 @@ codegen: base.v
 base.v: base.v.m4
 lint: base.v
 	verilator --lint-only base.v -I../spi -I../control_loop -I../waveform
+clean:
+	rm base.v

firmware/rtl/base/base.v.m4

@@ -1,5 +1,7 @@
 m4_changequote(`⟨', `⟩')
 m4_changecom(⟨/*⟩, ⟨*/⟩)
+m4_define(generate_macro, ⟨m4_define(M4_$1, $2)⟩)
+m4_include(../control_loop/control_loop_cmds.m4)
 /*********************************************************/
 /********************** M4 macros ************************/
 /*********************************************************/
@@ -132,7 +134,6 @@ m4_define(m4_adc_switch, ⟨
 /*********************** Verilog *************************/
 /*********************************************************/
 
-`include "control_loop_cmds.vh"
 module base #(
 	parameter DAC_PORTS = 2,
 m4_define(DAC_PORTS_CONTROL_LOOP, (DAC_PORTS + 1))
@@ -216,7 +217,7 @@ m4_define(CL_DATA_WID, CL_CONSTS_WID)
 	m4_adc_wires(ADC_TYPE1_WID, 7),
 
 	output cl_in_loop,
-	input [`CONTROL_LOOP_CMD_WIDTH-1:0] cl_cmd,
+	input [M4_CONTROL_LOOP_CMD_WIDTH-1:0] cl_cmd,
 	input [CL_DATA_WID-1:0] cl_word_in,
 	output reg [CL_DATA_WID-1:0] cl_word_out,
 	input cl_start_cmd,

firmware/rtl/common.makefile

@@ -1,3 +1,5 @@
 # Generate verilog from m4 file
 %.v: %.v.m4
-	m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
+	#m4 -P --synclines $< | awk -v filename=$< '/^#line/ {printf("`line %d %s 0\n", $$2, filename); next} {print}' > $@
+	# NOTE: f4pga yosys does not support `line directives. Use above for debug.
+	m4 -P $< > $@

firmware/rtl/control_loop/Makefile

@@ -15,8 +15,6 @@ E_WID=21
 
 test: obj_dir/Vcontrol_loop_sim_top obj_dir/Vcontrol_loop_math
 	# obj_dir/Vcontrol_loop_math
-clean:
-	rm -rf obj_dir *.fst
 
 obj_dir/Vcontrol_loop_math.mk: control_loop_math_sim.cpp ${COMMON} \
                                ${control_loop_math_verilog}
@@ -51,9 +49,13 @@ obj_dir/Vcontrol_loop_sim_top: obj_dir/Vcontrol_loop_sim_top.mk control_loop_cmd
 ####### Codegen ########
 
 include ../common.makefile
-codegen: control_loop_cmds.h boothmul.v control_loop_math.v control_loop.v control_loop_cmds.vh
+CODEGEN_FILES=control_loop_cmds.h boothmul.v control_loop_math.v control_loop.v control_loop_cmds.vh
+codegen: ${CODEGEN_FILES}
 control_loop_cmds.vh: control_loop_cmds.m4
 	m4 -P control_loop_cmds.vh.m4  > control_loop_cmds.vh
 control_loop_cmds.h: control_loop_cmds.m4
 	echo '#pragma once' > control_loop_cmds.h
 	m4 -P control_loop_cmds.h.m4 >> control_loop_cmds.h
+
+clean:
+	rm -rf obj_dir *.fst ${CODEGEN_FILES}

firmware/rtl/spi/Makefile

@@ -5,11 +5,15 @@
 all: test codegen
 test: obj_dir/Vspi_switch
 
-codegen: spi_master_ss_preprocessed.v spi_master_preprocessed.v \
+CODEGEN_FILES= spi_master_ss_preprocessed.v spi_master_preprocessed.v \
+	       spi_master_no_write_preprocessed.v \
+	       spi_master_no_read_preprocessed.v \
+               spi_master_ss_no_read_preprocessed.v \
                spi_master_ss_no_write_preprocessed.v spi_switch_preprocessed.v
 
+codegen: ${CODEGEN_FILES}
 %_preprocessed.v: %.v
-	verilator -E $< > $@
+	verilator -P -E $< > $@
 
 SRC= spi_switch.v spi_switch_sim.cpp
 obj_dir/Vspi_switch.mk: $(SRC)
@@ -20,4 +24,4 @@ obj_dir/Vspi_switch: obj_dir/Vspi_switch.mk $(SRC)
 	./obj_dir/Vspi_switch
 
 clean:
-	rm -rf obj_dir/
+	rm -rf obj_dir/ ${CODEGEN_FILES}

firmware/rtl/waveform/Makefile

@@ -4,10 +4,11 @@
 
 all: test codegen
 test: obj_dir/Vbram_interface_sim obj_dir/Vwaveform_sim
+CODEGEN_FILES=bram_interface_preprocessed.v waveform_preprocessed.v
 
-codegen: bram_interface_preprocessed.v waveform_preprocessed.v
+codegen: ${CODEGEN_FILES}
 %_preprocessed.v: %.v
-	verilator -E $< > $@
+	verilator -P -E $< > $@
 
 bram_SRC= bram_interface_sim.v dma_sim.v bram_interface.v bram_interface_sim.cpp
 
@@ -31,4 +32,4 @@ obj_dir/Vwaveform_sim: obj_dir/Vwaveform_sim.mk $(waveform_src)
 	./obj_dir/Vwaveform_sim
 
 clean:
-	rm -rf obj_dir/
+	rm -rf obj_dir/ ${CODEGEN_FILES}

firmware/soc.py

@@ -304,8 +304,11 @@ class CryoSNOM1SoC(SoCCore):
 		self.submodules.crg = _CRG(platform, sys_clk_freq, True)
 		platform.add_source("rtl/spi/spi_switch_preprocessed.v")
 		platform.add_source("rtl/spi/spi_master_preprocessed.v")
+		platform.add_source("rtl/spi/spi_master_no_write_preprocessed.v")
+		platform.add_source("rtl/spi/spi_master_no_read_preprocessed.v")
 		platform.add_source("rtl/spi/spi_master_ss_preprocessed.v")
 		platform.add_source("rtl/spi/spi_master_ss_no_write_preprocessed.v")
+		platform.add_source("rtl/spi/spi_master_ss_no_read_preprocessed.v")
 		platform.add_source("rtl/control_loop/sign_extend.v")
 		platform.add_source("rtl/control_loop/intsat.v")
 		platform.add_source("rtl/control_loop/boothmul.v")