csr to micropython
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parent
d76c1f8ad1
commit
5717ef59df
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@ -38,6 +38,7 @@ hardware-get:
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docker cp upsilon-hardware:/home/user/upsilon/gateware/build/digilent_arty/gateware/digilent_arty.bit ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/arty.dtb ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/csr.json ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/csr_bitwidth.json ../boot/
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hardware-clean:
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-docker container stop upsilon-hardware
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-docker container rm upsilon-hardware
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@ -25,5 +25,5 @@ arty.dts: csr.json
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arty.dtb: arty.dts
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dtc -O dtb -o arty.dtb arty.dts
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pin_io.c: csr.json generate_csr_locations.py
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python3 generate_csr_locations.py > pin_io.c
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mmio.py: csr2mp.py csr.json csr_bitwidth.json
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python3 csr2mp.py > mmio.py
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@ -0,0 +1,145 @@
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#!/usr/bin/python3
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# Copyright 2023 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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#######################################################################
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#
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# This file generates a Micropython module "mmio" with functions that
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# do raw reads and writes to MMIO registers.
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#
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# TODO: Devicetree?
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import json
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import sys
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class CSRGenerator:
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def __init__(self, csrjson, bitwidthjson, registers, outf):
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self.registers = registers
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self.csrs = json.load(open(csrjson))
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self.bws = json.load(open(bitwidthjson))
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self.file = outf
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def get_reg(self, name, num=None):
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""" Get the base address of the register. """
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if num is None:
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regname = f"base_{name}"
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else:
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regname = f"base_{name}_{num}"
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return self.csrs["csr_registers"][regname]["addr"]
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def get_accessor(self, name, num=None):
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""" Return a list of Micropython machine.mem accesses that can
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be used to read/write to a MMIO register.
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Since the Micropython API only supports accesses up to the
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natural word size of the processor, multiple accesses must be made
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for 64 bit registers.
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"""
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b = self.bws[name]
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if b <= 8:
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return [f'machine.mem8[{self.get_reg(name,num)}]']
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elif b <= 16:
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return [f'machine.mem16[{self.get_reg(name,num)}]']
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elif b <= 32:
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return [f'machine.mem32[{self.get_reg(name,num)}]']
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elif b <= 64:
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return [f'machine.mem32[{self.get_reg(name,num)}]',
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f'machine.mem32[{self.get_reg(name,num) + 4}]']
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else:
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raise Exception('unsupported width', b)
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def print(self, *args):
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print(*args, end='', file=self.file)
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def print_write_register(self, indent, varname, name, num):
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acc = self.get_accessor(name,num)
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if len(acc) == 1:
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self.print(f'{indent}{acc[0]} = {varname}\n')
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else:
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assert len(acc) == 2
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self.print(f'{indent}{acc[0]} = {varname} & 0xFFFFFFFF\n')
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self.print(f'{indent}{acc[1]} = {varname} >> 32\n')
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def print_read_register(self, indent, varname, name, num):
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acc = self.get_accessor(name,num)
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if len(acc) == 1:
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self.print(f'{indent}return {acc[0]}\n')
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else:
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assert len(acc) == 2
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self.print(f'{indent}return {acc[0]} | ({acc[1]} << 32)\n')
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def print_fun(self, optype, name, regnum, pfun):
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"""Print out a read/write function for an MMIO register.
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* {optype} is set to "read" or "write" (the string).
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* {name} is set to the name of the MMIO register, without number suffix.
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* {regnum} is set to the amount of that type oF MMIO register exists.
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* {pfun} is set to {self.print_write_register} or {self.print_read_register}
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"""
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self.print(f'def {optype}_{name}(')
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printed_argument = False
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if optype == 'write':
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self.print('val')
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printed_argument = True
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if regnum != 1:
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if printed_argument:
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self.print(', ')
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self.print('num')
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self.print('):\n')
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if regnum == 1:
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pfun('\t', 'val', name, None)
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else:
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for i in range(0,regnum):
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if i == 0:
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self.print(f'\tif ')
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else:
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self.print(f'\telif ')
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self.print(f'num == {i}:\n')
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pfun('\t\t', 'val', name, i)
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self.print(f'\telse:\n')
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self.print(f'\t\traise Exception("invalid {name}", regnum)\n')
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self.print('\n')
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def print_file(self):
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self.print('import machine\n')
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for reg in self.registers:
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self.print_fun('read', reg['name'], reg['total'], self.print_read_register)
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if not reg['read_only']:
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self.print_fun('write', reg['name'], reg['total'], self.print_write_register)
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if __name__ == "__main__":
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dac_num = 8
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adc_num = 8
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registers = [
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{"read_only": False, "name": "dac_sel", "total": dac_num},
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{"read_only": True, "name": "dac_finished", "total": dac_num},
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{"read_only": False, "name": "dac_arm", "total": dac_num},
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{"read_only": True, "name": "from_dac", "total": dac_num},
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{"read_only": False, "name": "to_dac", "total": dac_num},
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# {"read_only": False, "name": "wf_arm", "total": dac_num},
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# {"read_only": False, "name": "wf_halt_on_finish", "total": dac_num},
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# {"read_only": True, "name": "wf_finished", "total": dac_num},
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# {"read_only": True, "name": "wf_running", "total": dac_num},
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# {"read_only": False, "name": "wf_time_to_wait", "total": dac_num},
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# {"read_only": False, "name": "wf_refresh_start", "total": dac_num},
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# {"read_only": True, "name": "wf_refresh_finished", "total": dac_num},
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# {"read_only": False, "name": "wf_start_addr", "total": dac_num},
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{"read_only": True, "name": "adc_finished", "total": adc_num},
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{"read_only": False, "name": "adc_arm", "total": adc_num},
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{"read_only": True, "name": "from_adc", "total": adc_num},
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{"read_only": False, "name": "adc_sel", "total": adc_num},
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{"read_only": True, "name": "cl_in_loop", "total": 1},
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{"read_only": False, "name": "cl_cmd", "total": 1},
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{"read_only": False, "name": "cl_word_in", "total": 1},
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{"read_only": False, "name": "cl_word_out", "total": 1},
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{"read_only": False, "name": "cl_start_cmd", "total": 1},
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{"read_only": True, "name": "cl_finish_cmd", "total": 1},
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]
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CSRGenerator("csr.json", "csr_bitwidth.json", registers, sys.stdout).print_file()
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@ -1,144 +0,0 @@
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#!/usr/bin/python3
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import json
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import sys
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"""
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This file uses csr.json and csr_bitwidth.json and writes functions
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that handle reads and writes to MMIO.
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"""
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class CSRGenerator:
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def __init__(self, csrjson, bitwidthjson, registers, outf, dacmax, adcmax):
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self.registers = registers
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self.csrs = json.load(open(csrjson))
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self.bws = json.load(open(bitwidthjson))
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self.file = outf
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self.dacmax = dacmax
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self.adcmax = adcmax
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def get_reg(self, name, num):
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if num is None:
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regname = f"base_{name}"
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else:
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regname = f"base_{name}_{num}"
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return self.csrs["csr_registers"][regname]["addr"]
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def get_bitwidth_type(self, name):
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b = self.bws[name]
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if b <= 8:
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return 8
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elif b <= 16:
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return 16
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elif b <= 32:
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return 32
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elif b <= 64:
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return 64
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else:
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raise Exception('unsupported width', b)
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def print(self, *args):
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print(*args, end='', file=self.file)
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def print_write_fun(self, name, regnum):
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typ = self.get_bitwidth_type(name)
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self.print('static inline void\n')
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self.print(f'write_{name}(uint{typ}_t v')
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if regnum != 1:
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self.print(f', int num')
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self.print(')\n{\n')
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if regnum != 1:
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self.print('\t', f'static const uintptr_t loc[{regnum}]', '= {\n')
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self.print('\t\t', self.get_reg(name,0), '\n')
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for i in range(1,regnum):
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self.print('\t\t,', self.get_reg(name, i), '\n')
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self.print('\t};\n')
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self.print('''
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if (num < 0 || num >= ARRAY_SIZE(loc)) {
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LOG_ERR("invalid location %d", num);
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k_fatal_halt(K_ERR_KERNEL_OOPS);
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}
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''')
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self.print('\t', f'litex_write{typ}(v, {"loc[num]" if regnum != 1 else self.get_reg(name, None)});', '\n}\n\n')
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def print_read_fun(self, name, regnum):
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typ = self.get_bitwidth_type(name)
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self.print(f'static inline uint{typ}_t\nread_{name}')
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if regnum != 1:
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self.print(f'(int num)', '\n{\n')
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else:
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self.print('(void)\n{\n')
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if regnum != 1:
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self.print('\t', f'static const uintptr_t loc[{regnum}]', '= {\n')
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self.print('\t\t', self.get_reg(name,0), '\n')
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for i in range(1,regnum):
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self.print('\t\t,', self.get_reg(name, i), '\n')
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self.print('\t};\n')
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self.print('''
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if (num < 0 || num >= ARRAY_SIZE(loc)) {
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LOG_ERR("invalid location %d", num);
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k_fatal_halt(K_ERR_KERNEL_OOPS);
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}
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''')
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self.print('\t', f'return litex_read{typ}({"loc[num]" if regnum != 1 else self.get_reg(name, None)}', ');\n}\n\n')
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def print_file(self):
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self.print('''
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#pragma once
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static inline void litex_write64(uint64_t value, unsigned long addr)
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{
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#if CONFIG_LITEX_CSR_DATA_WIDTH >= 32
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sys_write32(value >> 32, addr);
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sys_write32(value, addr + 0x4);
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#else
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# error Unsupported CSR data width
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#endif
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}
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''')
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self.print('#define DAC_MAX', self.dacmax, '\n')
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self.print('#define ADC_MAX', self.adcmax, '\n')
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for reg in self.registers:
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self.print_read_fun(reg[1],reg[2])
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if not reg[0]: #read only
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self.print_write_fun(reg[1],reg[2])
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if __name__ == "__main__":
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dac_num = 8
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adc_num = 8
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registers = [
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# Read-only, name, number
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(False, "dac_sel", dac_num),
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(True, "dac_finished", dac_num),
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(False, "dac_arm", dac_num),
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(True, "from_dac", dac_num),
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(False, "to_dac", dac_num),
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# (False, "wf_arm", dac_num),
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# (False, "wf_halt_on_finish", dac_num),
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# (True, "wf_finished", dac_num),
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# (True, "wf_running", dac_num),
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# (False, "wf_time_to_wait", dac_num),
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# (False, "wf_refresh_start", dac_num),
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# (True, "wf_refresh_finished", dac_num),
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# (False, "wf_start_addr", dac_num),
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(True, "adc_finished", adc_num),
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(False, "adc_arm", adc_num),
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(True, "from_adc", adc_num),
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(False, "adc_sel", adc_num),
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(True, "cl_in_loop", 1),
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(False, "cl_cmd", 1),
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(False, "cl_word_in", 1),
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(False, "cl_word_out", 1),
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(False, "cl_start_cmd", 1),
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(True, "cl_finish_cmd", 1),
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]
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CSRGenerator("csr.json", "csr_bitwidth.json", registers, sys.stdout, dac_num, adc_num).print_file()
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