From 60404cd0264e0231b6bad0dbcdd77c08a271ef6d Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Sat, 17 Dec 2022 10:18:15 -0500
Subject: [PATCH] ram_fifo.v: add simulator debugging checks

---
 firmware/rtl/raster/ram_fifo.v | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/firmware/rtl/raster/ram_fifo.v b/firmware/rtl/raster/ram_fifo.v
index ac136c1..adb3709 100644
--- a/firmware/rtl/raster/ram_fifo.v
+++ b/firmware/rtl/raster/ram_fifo.v
@@ -10,6 +10,7 @@ module ram_fifo #(
 	input write_enable,
 
 	input signed [DAT_WID-1:0] write_dat,
+	output reg [FIFO_DEPTH_WID-1:0] fifo_size,
 	output signed [DAT_WID-1:0] read_dat
 );
 
@@ -27,4 +28,24 @@ ram_fifo_dual_port #(
 	.read_dat(read_dat)
 );
 
+always @ (posedge clk) begin
+	if (rst) begin
+		fifo_size <= 0;
+	end else if (read_enable && !write_enable) begin
+		fifo_size <= fifo_size - 1;
+`ifdef VERILATOR
+		if (fifo_size == 0) begin
+			$error("fifo underflow");
+		end
+`endif
+	end else if (write_enable && !read_enable) begin
+		fifo_size <= fifo_size + 1;
+`ifdef VERILATOR
+		if (fifo_size == FIFO_DEPTH) begin
+			$error("fifo overflow");
+		end
+`endif
+	end
+end
+
 endmodule