raster work

firmware/rtl/raster/APACHE_LICENSE

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firmware/rtl/raster/Makefile

@@ -0,0 +1,13 @@
+# Makefile for tests and hardware verification.
+
+.PHONY: test clean
+
+RAM_FIFO_SRC= ram_fifo.v ram_fifo_sim.cpp FIFO36E1.v
+
+obj_dir/Vram_fifo.mk:
+	verilator --cc --exe -Wall --trace --trace-fst \
+		${RAM_FIFO_SRC}
+obj_dir/Vram_fifo: obj_dir/Vram_fifo.mk
+	cd obj_dir && make -f Vram_fifo.mk
+test: obj_dir/Vram_fifo
+	./obj_dir/Vram_fifo

firmware/rtl/raster/ram_fifo.v

@@ -0,0 +1,52 @@
+/* YOSYS has a difficult time infering single port BRAM. It can infer
+ * double-port block ram, however. This module is written as a double
+ * port block ram, even though both clocks will end up being the same.
+ * TODO:
+ *   "empty" and "full" status indiciators for simulation
+
+ * https://stackoverflow.com/questions/62703942/trouble-getting-yosys-to-infer-block-ram-array-rather-than-using-logic-cells-v
+ * The answer by "TinLethax" infers a BRAM.
+ */
+module ram_fifo #(
+	parameter DAT_WID = 24,
+	parameter FIFO_DEPTH = 1500,
+	parameter FIFO_DEPTH_WID = 11
+) (
+	input RCLK,
+	input WCLK,
+	input rst,
+
+	input read_enable,
+	input write_enable,
+
+	input signed [DAT_WID-1:0] write_dat,
+	output reg signed [DAT_WID-1:0] read_dat
+);
+
+reg [DAT_WID-1:0] memory [FIFO_DEPTH-1:0];
+initial memory[0] <= 24'b0;
+
+/* Read domain */
+
+reg [FIFO_DEPTH_WID-1:0] read_ptr = 0;
+always @ (posedge RCLK) begin
+	if (rst) begin
+		read_ptr <= 0;
+	end else if (read_enable) begin
+		read_dat <= memory[read_ptr];
+		read_ptr <= read_ptr + 1;
+	end
+end
+
+/* Write domain */
+reg [FIFO_DEPTH_WID-1:0] write_ptr = 0;
+always @ (posedge WCLK) begin
+	if (rst) begin
+		write_ptr <= 0;
+	if (write_enable) begin
+		memory[write_ptr] <= write_dat;
+		wite_dat <= writr_dat + 1;
+	end
+end
+
+endmodule

firmware/rtl/raster/ram_fifo_sim.cpp

@@ -0,0 +1,91 @@
+#include <memory>
+#include <limits>
+#include <cstdint>
+#include <cstring>
+#include <cstdlib>
+#include <iostream>
+#include <random>
+#include <unistd.h>
+
+#include <verilated.h>
+#include "Vraster_sim.h"
+using ModType = Vram_fifo;
+ModType *mod;
+
+uint32_t main_time = 0;
+
+static void run_clock() {
+	for (int i = 0; i < 2; i++) {
+		mod->clk = !mod->clk;
+		mod->eval();
+		main_time++;
+	}
+}
+
+static void cleanup_exit() {
+	mod->final();
+	delete mod;
+}
+
+static void init(int argc, char **argv) {
+	Verilated::commandArgs(argc, argv);
+	Verilated::traceEverOn(true);
+	mod = new ModType;
+	mod->clk = 0;
+	atexit(cleanup_exit);
+}
+
+static void push(uint32_t v) {
+	if (mod->full) {
+		fprintf(stderr, "Fifo full at push %d\n", i);
+		exit(1);
+	}
+	mod->in_dat = v;
+	mod->write_enable = 1;
+	while (!mod->write_fin)
+		run_clock();
+	mod->write_enable = 0;
+	run_clock();
+}
+
+static void pop(int i) {
+	if (mod->empty) {
+		fprintf(stderr, "Fifo empty at pop %d\n", i);
+		exit(1);
+	}
+	mod->read_enable = 1;
+	while (!mod->read_fin)
+		run_clock();
+	mod->read_enable = 0;
+	run_clock();
+}
+
+#define MAX_VALS 32000/24
+uint32_t vals[MAX_VALS];
+
+int main(int argc, char **argv) {
+	init(argc, argv);
+	init_values();
+
+	mod->rst = 0;
+	mod->read_enable = 0;
+	mod->write_enable = 0;
+	mod->in_dat = 0;
+	run_clock();
+
+	/* Simple test */
+	for (int i = 0; i < MAX_VALS; i++) {
+		vals[i] = rand() & 0xFFFFFFFFFFFF;
+		push(vals[i], i);
+	}
+
+	for (int i = 0; i < MAX_VALS; i++) {
+		pop(i);
+		if (mod->out_dat != vals[i]) {
+			fprintf(stderr, "expect %u, %u\n", vals[i], mod->out_dat);
+			return 1;
+		}
+	}
+
+	return 0;
+}

firmware/rtl/raster/ram_shim.v

@@ -1,7 +1,16 @@
 /* Ram shim. This is an interface designed for a LiteX RAM
  * DMA module. It can also be connected to a simulator.
  *
+ * The read end is implemented in C since all of this is
+ * backed by memory.
+ *
  * THIS MODULE ASSUMES that RAM_WORD < DAT_WID < RAM_WORD*2.
+ *
+ * TODO: Buffer the data (using something like block ram) and
+ * write it out asynchronously. This will require instantiating
+ * the block ram primitive directly for Yosys. This should make
+ * writes to RAM smoother, and reads smoother when the CPU is
+ * reading the data.
  */
 module ram_shim #(
 	parameter BASE_ADDR = 32'h1000000,
@@ -15,6 +24,15 @@ module ram_shim #(
 	input commit,
 	output reg finished,
 
+	/* Used by the kernel code to request the current
+	 * location of the FIFO head. Used to memcpy data,
+	 * it might better than repeatedly calling a FIFO
+	 * read.
+	 */
+	input read_end_req_off,
+	output reg [RAM_WID-1:0] read_end_addr,
+	output reg read_end_req_valid,
+
 	output reg [RAM_WORD-1:0] word,
 	output [RAM_WID-1:0] addr,
 	output reg write,
@@ -29,6 +47,16 @@ reg [2:0] state = WAIT_ON_COMMIT;
 
 reg [MAX_BYTE_WID-1:0] offset = 0;
 assign addr = BASE_ADDR + {{(RAM_WID - MAX_BYTE_WID){1'b0}}, offset};
+initial read_end_req_valid = 0;
+
+always @ (posedge clk) begin
+	if (read_end_req_off && !read_end_req_valid) begin
+		read_end_req_valid = 1;
+		read_end_addr <= addr;
+	end else if (read_end_req_valid && !read_end_req_off) begin
+		read_end_req_valid <= 0;
+	end
+end
 
 always @ (posedge clk) begin
 	case (state)

firmware/rtl/raster/raster.v

@@ -13,8 +13,6 @@ module raster #(
 	output reg finished,
 	output reg running,
 
-	/* Amount of steps per sample. */
-	input [STEPWID-1:0] steps_per_sample_in,
 	/* Amount of samples in one line (forward) */
 	input [SAMPLEWID-1:0] max_samples_in,
 	/* Amount of lines in the output. */
@@ -27,10 +25,6 @@ module raster #(
 	input signed [DAC_DATA_WID-1:0] dx_in,
 	input signed [DAC_DATA_WID-1:0] dy_in,
 
-	/* Vertical steps to go to the next line. */
-	input signed [DAC_DATA_WID-1:0] dx_vert_in,
-	input signed [DAC_DATA_WID-1:0] dy_vert_in,
-
 	/* X and Y DAC piezos */
 	output x_arm,
 	output [DAC_WID-1:0] x_to_dac,
@@ -124,8 +118,8 @@ reg [STATE_WID-1:0] state = WAIT_ON_ARM;
 reg [SAMPLEWID-1:0] sample = 0;
 reg [SAMPLEWID-1:0] line = 0;
 reg [TIMER_WID-1:0] counter = 0;
-reg [DAC_DATA_WID-1:0] x_val = 0;
+reg signed [DAC_DATA_WID-1:0] x_val = 0;
-reg [DAC_DATA_WID-1:0] y_val = 0;
+reg signed [DAC_DATA_WID-1:0] y_val = 0;
 
 /* Buffer to store all measured ADC values. This
  * is shifted until it is all zeros to determine
@@ -143,8 +137,6 @@ reg [ADCNUM-1:0] adc_used = 0;
 reg is_reverse = 0;
 reg signed [DAC_DATA_WID-1:0] dx = 0;
 reg signed [DAC_DATA_WID-1:0] dy = 0;
-reg signed [DAC_DATA_WID-1:0] dx_vert = 0;
-reg signed [DAC_DATA_WID-1:0] dy_vert = 0;
 reg [TIMER_WID-1:0] settle_time = 0;
 
 reg [SAMPLEWID-1:0] max_samples = 0;
@@ -171,11 +163,8 @@ always @ (posedge clk) begin
 		adc_used <= adc_used_in;
 		dx <= dx_in;
 		dy <= dy_in;
-		dx_vert <= dx_vert_in;
-		dy_vert <= dy_vert_in;
 		max_samples <= max_samples_in;
 		max_lines <= max_lines_in;
-		steps_per_sample <= steps_per_sample_in;
 		settle_time <= settle_time_in;
 
 		is_reverse <= 0;
@@ -289,10 +278,11 @@ always @ (posedge clk) begin
 				finished <= 1;
 				running <= 0;
 			end else begin
-				x_val <= x_val + dx_vert;
+				/* rotation of (dx,dy) by 90° -> (dy, -dx) */
+				x_val <= x_val + dy;
 				x_to_dac <= {4'b0001, x_val + dx_vert};
 				x_arm <= 1;
-				y_val <= y_val + dy_vert;
+				y_val <= y_val - dx;
 				y_to_dac <= {4'b0001, y_val + dy_vert};
 				y_arm <= 1;
 				line <= line + 1;

firmware/rtl/raster/raster_sim.cpp

@@ -0,0 +1,109 @@
+#include <memory>
+#include <limits>
+#include <cstdint>
+#include <cstring>
+#include <cstdlib>
+#include <iostream>
+#include <random>
+#include <unistd.h>
+
+#include <verilated.h>
+#include "Vraster_sim.h"
+using ModType = Vraster_sim;
+ModType *mod;
+
+uint32_t main_time = 0;
+
+static void run_clock() {
+	for (int i = 0; i < 2; i++) {
+		mod->clk = !mod->clk;
+		mod->eval();
+		main_time++;
+	}
+}
+
+static void cleanup_exit() {
+	mod->final();
+	delete mod;
+}
+
+static void init(int argc, char **argv) {
+	Verilated::commandArgs(argc, argv);
+	Verilated::traceEverOn(true);
+	mod = new ModType;
+	mod->clk = 0;
+	atexit(cleanup_exit);
+}
+
+static void init_values() {
+	mod->arm = 0;
+	mod->max_samples_in = 512;
+	mod->max_lines_in = 512;
+	/* Settle time is 1 μs */
+	mod->settle_time_in = 100;
+
+	mod->dx_in = 17;
+	mod->dy_in = 13;
+	mod->coord_dac[0] = 0;
+	mod->coord_dac[1] = 0;
+
+	for (int i = 0; i < ADCNUM; i++)
+		mod->adc_data[i] = 0;
+	mod->adc_finished = 0;
+	mod->adc_used_in = 0;
+
+	mod->ram_valid = 0;
+}
+
+uint32_t *measured_values[ADCNUM];
+
+static void init_measurements() {
+	std::default_random_engine generator{};
+	std::normal_distribution<> dist{10000, 100};
+	std::random_device rd;
+
+	for (int i = 0; i < ADCNUM; i++) {
+		generator.seed(rd());
+		measured_values[i] = new int32_t[mod->max_lines_in][mod->max_samples_in];
+		for (int j = 0; j < mod->max_lines_in; j++) {
+			for (int k = 0; k < mod->max_samples_in; k++) {
+				measured_values[i][j][k] = dist(generator);
+			}
+		}
+	}
+}
+
+static void deinit_measurement() {
+	for (int i = 0; i < ADCNUM; i++) {
+		delete measured_values[i];
+	}
+}
+
+static std::array<uint16_t, 1 << MAX_BYTE_WID> fifo;
+static uint32_t read_pos, write_pos;
+
+static void handle_ram() {
+}
+
+static void handle_adc() {
+	static int cntr[ADCNUM] = {0};
+	static bool measuring[ADCNUM] = {0};
+
+	for (int i = 0; i < ADCNUM; i++) {
+		if (mod->adc_used_in & 1) {
+}
+
+int main(int argc, char **argv) {
+	init(argc, argv);
+	init_values();
+	init_measurements();
+	run_clock();
+
+	mod->arm = 1;
+	while (!mod->finished) {
+		run_clock();
+		handle_ram();
+	}
+
+	return 0;
+}

firmware/rtl/raster/raster_sim.v

@@ -1,3 +1,4 @@
+`timescale 10ns/10ns
 module raster_sim #(
 	parameter SAMPLEWID = 9,
 	parameter DAC_DATA_WID = 20,
@@ -12,15 +13,16 @@ module raster_sim #(
 	parameter MAX_BYTE_WID = 13,
 	parameter DAT_WID = 24,
 	parameter RAM_WORD = 16,
-	parameter RAM_WID = 32
+	parameter RAM_WID = 32,
+
+	parameter RAM_SIM_WAIT_TIME = 54,
+	parameter ADC_SIM_WAIT_TIME = 54
 ) (
 	input clk,
 	input arm,
 	output reg finished,
 	output reg running,
 
-	/* Amount of steps per sample. */
-	input [STEPWID-1:0] steps_per_sample_in,
 	/* Amount of samples in one line (forward) */
 	input [SAMPLEWID-1:0] max_samples_in,
 	/* Amount of lines in the output. */
@@ -37,18 +39,7 @@ module raster_sim #(
 	input signed [DAC_DATA_WID-1:0] dx_vert_in,
 	input signed [DAC_DATA_WID-1:0] dy_vert_in,
 
-	/* X and Y DAC piezos */
+	output reg [DAC_DATA_WID-1:0] coord_dac [1:0],
-	output x_arm,
-	output [DAC_WID-1:0] x_to_dac,
-	/* verilator lint_off UNUSED */
-	input [DAC_WID-1:0] x_from_dac,
-	input x_finished,
-
-	output y_arm,
-	output [DAC_WID-1:0] y_to_dac,
-	/* verilator lint_off UNUSED */
-	input [DAC_WID-1:0] y_from_dac,
-	input y_finished,
 
 	/* Connections to all possible ADCs. These are connected to SPI masters
 	 * and they will automatically extend ADC value lengths to their highest
@@ -63,14 +54,95 @@ module raster_sim #(
 	/* DMA interface */
 	output [RAM_WORD-1:0] word,
 	output [RAM_WID-1:0] addr,
-	output ram_write,
+	output reg ram_write,
 	input ram_valid
 );
 
+/**** DAC simulation ****/
+
+reg [DAC_WID-1:0] coord_write_buf [1:0];
+reg [DAC_WID-1:0] coord_to_dac [1:0];
+reg [DAC_WID-1:0] coord_from_dac [1:0];
+wire coord_arm [1:0];
+reg coord_finished [1:0];
+
+genvar ci;
+generate for (ci = 0; ci < 2; ci = ci + 1) begin
+	initial begin
+		coord_write_buf[ci] = 0;
+		coord_to_dac[ci] = 0;
+		coord_from_dac[ci] = 0;
+		coord_finished[ci] = 0;
+	end
+
+	always @ (posedge clk) begin
+		if (coord_arm[ci] && !coord_finished[ci]) begin
+			coord_to_dac[ci] <= coord_write_buf[ci];
+			coord_finished[ci] <= 1;
+
+			case (coord_from_dac[ci][DAC_WID-1:DAC_WID-4])
+			4'b1001: begin
+				coord_write_buf[ci] <= {4'b1001, coord_dac[ci]};
+			end
+			4'b0001: begin
+				coord_write_buf[ci] <= 0;
+				coord_dac[ci] <= coord_from_dac[ci][DAC_WID-4-1:0];
+			end
+			endcase
+
+		end else if (!coord_arm[ci]) begin
+			coord_finished[ci] <= 0;
+		end
+	end
+end endgenerate
+
+/**** ADC Shim ****/
+
+wire adc_arm_internal;
+reg [31:0] adc_wait_cntr = 0;
+
+always @ (posedge clk) begin
+	if (adc_arm_internal != 0) begin
+		if (adc_wait_cntr < ADC_SIM_WAIT_TIME) begin
+			adc_wait_cntr <= adc_wait_cntr + 1;
+		end else begin
+			adc_arm <= adc_arm_internal;
+		end
+	end else begin
+		adc_wait_cntr <= 0;
+	end
+end
+
+/**** RAM Shim ****/
+
+/* Check all addresses are valid. */
+property address_in_range;
+	@(posedge clk)
+	ram_commit |->
+	BASE_ADDR <= addr && addr < BASE_ADDR + (1 << MAX_BYTE_WID);
+endproperty
+address_in_range_assert: assert property (address_in_range);
+
 wire signed [DAT_WID-1:0] ram_data;
 wire ram_commit;
 wire ram_write_finished;
 
+wire ram_write_internal = 0;
+reg [31:0] ram_cntr = 0;
+
+always @ (posedge clk) begin
+	if (ram_commit) begin
+		if (ram_cntr < RAM_SIM_WAIT_TIME) begin
+			ram_cntr <= ram_cntr + 1;
+		end else begin
+			ram_write <= 1;
+		end
+	end else begin
+		ram_cntr <= 0;
+		ram_write <= 0;
+	end
+end
+
 ram_shim #(
 	.BASE_ADDR(BASE_ADDR),
 	.MAX_BYTE_WID(MAX_BYTE_WID),
@@ -84,7 +156,7 @@ ram_shim #(
 	.finished(ram_write_finished),
 	.word(word),
 	.addr(addr),
-	.write(ram_write),
+	.write(ram_write_internal),
 	.valid(ram_valid)
 );
 
@@ -120,7 +192,7 @@ raster #(
 	.y_from_dac(y_from_dac),
 	.y_finished(y_finished),
 
-	.adc_arm(adc_arm),
+	.adc_arm(adc_arm_internal),
 	.adc_data(adc_data),
 	.adc_finished(adc_finished),