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add assertions

This commit is contained in:
Peter McGoron 2023-04-02 21:25:19 +00:00
parent 66ea3ca0ea
commit 69f16264dd
1 changed files with 40 additions and 20 deletions
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38
firmware/rtl/waveform/waveform.v
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@ -21,6 +21,7 @@ module waveform #(
input arm, input arm,
input halt_on_finish, input halt_on_finish,
output reg finished, output reg finished,
output running,
input [TIMER_WID-1:0] time_to_wait, input [TIMER_WID-1:0] time_to_wait,
/* User interface */ /* User interface */
@ -98,10 +99,13 @@ localparam WAIT_ON_ARM = 0;
localparam DO_WAIT = 1; localparam DO_WAIT = 1;
localparam RECV_WORD = 2; localparam RECV_WORD = 2;
localparam WAIT_ON_DAC = 3; localparam WAIT_ON_DAC = 3;
reg [1:0] state = WAIT_ON_ARM; localparam WAIT_ON_DISARM = 4;
reg [2:0] state = WAIT_ON_ARM;
reg [TIMER_WID-1:0] wait_timer = 0; reg [TIMER_WID-1:0] wait_timer = 0;
assign running = state != WAIT_ON_ARM;
always @ (posedge clk) case (state) always @ (posedge clk) case (state)
WAIT_ON_ARM: begin WAIT_ON_ARM: begin
finished <= 0; finished <= 0;
@ -121,26 +125,42 @@ end else if (wait_timer == 0) begin
end else begin end else begin
wait_timer <= wait_timer - 1; wait_timer <= wait_timer - 1;
end end
RECV_WORD: if (word_ok) begin RECV_WORD: begin
`ifdef VERILATOR
if (!word_next) begin
$error("RECV_WORD: word_next not asserted means hang");
end
`endif
if (word_ok) begin
dac_out <= {4'b0001, word}; dac_out <= {4'b0001, word};
dac_arm <= 1; dac_arm <= 1;
word_next <= 0; word_next <= 0;
state <= WAIT_ON_DAC; state <= WAIT_ON_DAC;
end
end end
WAIT_ON_DAC: if (dac_finished) begin WAIT_ON_DAC: begin
`ifdef VERILATOR
if (!dac_arm) begin
$error("WAIT_ON_DAC: dac_arm not asserted means hang");
end
`endif
if (dac_finished) begin
dac_arm <= 0; dac_arm <= 0;
/* Was the last word read *the* last word? */ /* Was the last word read *the* last word? */
if (word_last) begin if (word_last && halt_on_finish) begin
if (!halt_on_finish) begin state <= WAIT_ON_DISARM;
state <= WAIT_ON_ARM;
finished <= 0;
end else begin
finished <= 1; finished <= 1;
end
end else begin end else begin
state <= DO_WAIT; state <= DO_WAIT;
wait_timer <= time_to_wait;
end end
end
end
WAIT_ON_DISARM: if (!arm) begin
state <= WAIT_ON_ARM;
end end
endcase endcase