sketch out raster scan
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@ -2,59 +2,80 @@ module raster #(
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parameter SAMPLEWID = 9,
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parameter DAC_DATA_WID = 20,
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parameter DAC_WID = 24,
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parameter DAC_WAIT_BETWEEN_CMD = 10,
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parameter TIMER_WID = 4,
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parameter STEPWID = 16,
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parameter MAX_ADC_DATA_WID = 24
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) (
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input clk,
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input arm,
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output reg finshed,
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output reg running,
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/* Amount of steps per sample. */
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input [STEPWID-1:0] steps,
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input [STEPWID-1:0] steps_per_sample_in,
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/* Amount of samples in one line (forward) */
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input [SAMPLEWID-1:0] samples,
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input [SAMPLEWID-1:0] max_samples_in,
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/* Amount of lines in the output. */
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input [SAMPLEWID-1:0] lines,
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input [SAMPLEWID-1:0] max_lines_in,
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/* Wait time after each step. */
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input [TIMER_WID-1:0] settle_time,
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/* Each step goes (x,y) -> (dx,dy) forward for each line of
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/* Each step goes (x,y) -> (x + dx, y + dy) forward for each line of
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* the output. */
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input signed [DAC_DATA_WID-1:0] dx,
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input signed [DAC_DATA_WID-1:0] dy,
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input signed [DAC_DATA_WID-1:0] dx_in,
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input signed [DAC_DATA_WID-1:0] dy_in,
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/* Vertical steps to go to the next line. */
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input signed [DAC_DATA_WID-1:0] dx_vert,
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input signed [DAC_DATA_WID-1:0] dy_vert,
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input signed [DAC_DATA_WID-1:0] dx_vert_in,
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input signed [DAC_DATA_WID-1:0] dy_vert_in,
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/* X and Y DAC piezos */
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input x_ready,
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output [DACWID-1:0] x_to_dac,
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input [DACWID-1:0] x_from_dac,
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output x_arm,
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output [DAC_DATA_WID-1:0] x_to_dac,
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input [DAC_DATA_WID-1:0] x_from_dac,
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output x_finished,
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input y_ready,
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output [DACWID-1:0] y_to_dac,
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input [DACWID-1:0] y_from_dac,
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output y_arm,
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output [DAC_DATA_WID-1:0] y_to_dac,
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input [DAC_DATA_WID-1:0] y_from_dac,
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output y_finished,
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/* Connections to all possible ADCs. These are connected to SPI masters
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* and they will automatically extend ADC value lengths to their highest
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* values. */
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input adc_in [0:ADCNUM-1],
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output [MAX_ADC_DATA_WID-1:0] adc_conv [0:ADCNUM-1],
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output adc_finished [0:ADCNUM-1],
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output reg [ADCNUM-1:0] adc_arm,
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input [MAX_ADC_DATA_WID-1:0] adc_data [ADCNUM-1:0],
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input [ADCNUM-1:0] adc_finished,
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/* Bitmap for which ADCs are used. */
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input [ADCNUM-1:0] adc_used,
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input [ADCNUM-1:0] adc_used_in,
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output signed [MAX_ADC_DATA_WID-1:0] fifo_data,
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output fifo_ready,
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input fifo_valid
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/* RAM DMA. This is generally not directly connected to the
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* DMA IP. A shim is used in order to write multiple words
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* to memory. */
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output reg [MAX_ADC_DATA_WID-1:0] data,
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output reg mem_commit,
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input mem_finished
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);
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/* During a scan, some of the ADCs will be scanned, but some will not.
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* The data are packed in such a way so that the most significant
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* word will contain the highest enabled ADC number, and the least
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* significant word will contain the lowest enabled ADC number (and so
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* on in between).
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*
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* There's not a good way to precalculate this so instead the check
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* is done at each "send" stage.
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*/
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/* State machine:
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┏━━━━ WAIT ON ARM
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↑ ↓ (arm -> 1)
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┃ GET DAC VALUES
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┃ ↓ (when x and y values are obtained)
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┃ REQUEST DAC VALUES
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┃ ↓ (when x and y values are requested)
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┃ OBTAIN DAC VALUES
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┃ ↓ (when x and y values are measured)
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┃ ┏━LOOP FORWARD WITHOUT MEASUREMENT
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┃ ↑ ↓ (when enough steps are taken)
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┃ ┃ GET ADC VALUES
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@ -84,18 +105,210 @@ module raster #(
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localparam WAIT_ON_ARM = 0;
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localparam GET_DAC_VALUES = 1;
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localparam INCREMENT_XVAL = 2;
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localparam GET_ADC_VAL = 3;
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localparam SEND_FIFO = 4;
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localparam WAIT_FOR_REARM = 5;
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localparam REQUEST_DAC_VALUES = 2;
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localparam MEASURE = 3;
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localparam SCAN_ADC_VALUES = 4;
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localparam SEND_VALUE = 5;
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localparam ADVANCE_DAC_WRITE = 6;
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localparam WAIT_ADVANCE = 7;
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localparam ON_ADC_FINISHED = 8;
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localparam NEXT_LINE = 9;
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localparam WAIT_ON_ARM_DEASSERT = 10;
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localparam STATE_WID = 4;
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reg [2:0] stepstate = WAIT_ON_ARM;
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reg is_forward = 1;
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reg [SAMPLEWID-1:0] samplenum;
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reg [STEPWID-1:0] stepnum;
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/********** Loop State ***********/
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reg [STATE_WID-1:0] state = WAIT_ON_ARM;
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reg [SAMPLEWID-1:0] sample = 0;
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reg [SAMPLEWID-1:0] line = 0;
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reg [TIMER_WID-1:0] counter = 0;
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reg [DAC_DATA_WID-1:0] x_val = 0;
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reg [DAC_DATA_WID-1:0] y_val = 0;
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/* Buffer to store all measured ADC values. This
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* is shifted until it is all zeros to determine
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* which ADC values should be read off.
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*/
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reg [ADCNUM-1:0] adc_used_tmp = 0;
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/* Buffer to store ADC data. The buffers are permuted in order
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* for the design to read off the proper values into RAM.
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*/
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reg [MAX_ADC_DATA_WID-1:0] adc_data_tmp [ADCNUM-1:0];
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/********** Loop Parameters *************/
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reg [ADCNUM-1:0] adc_used_in = 0;
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reg is_reverse = 0;
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reg signed [DAC_DATA_WID-1:0] dx = 0;
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reg signed [DAC_DATA_WID-1:0] dy = 0;
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reg signed [DAC_DATA_WID-1:0] dx_vert = 0;
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reg signed [DAC_DATA_WID-1:0] dy_vert = 0;
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reg [SAMPLEWID-1:0] max_samples = 0;
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reg [SAMPLEWID-1:0] max_lines = 0;
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reg [STEPWID-1:0] steps_per_sample = 0;
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/* Reading ADC data.
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* If this doesn't work, a gigantic vector with large bit shifts
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* can also work.
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*/
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genvar ii;
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generate for (ii = 0; ii < ADCNUM - 1; ii = ii + 1) begin
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always @ (posedge clk) begin
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if (state == SCAN_ADC_VALUES) begin
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adc_data_tmp[ii] <= adc_data_tmp[ii+1];
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end
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end
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end endgenerate
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always @ (posedge clk) begin
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case (state)
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WAIT_ON_ARM: begin if (arm) begin
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if (adc_used_in != 0) begin
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state <= REQUEST_DAC_VALUES;
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end
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adc_used <= adc_used_in;
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dx <= dx_in;
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dy <= dy_in;
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dx_vert <= dx_vert_in;
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dy_vert <= dy_vert_in;
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max_samples <= max_samples_in;
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max_lines <= max_lines_in;
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steps_per_sample <= steps_per_sample_in;
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is_reverse <= 0;
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sample <= 0;
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line <= 0;
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x_to_dac <= {4'b1001, 20'b0};
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y_to_dac <= {4'b1001, 20'b0};
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x_arm <= 1;
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y_arm <= 1;
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adc_arm <= 0;
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end else begin
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running <= 0;
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end end
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REQUEST_DAC_VALUES: begin
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if (x_finished && y_finished) begin
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x_to_dac <= 0;
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y_to_dac <= 0;
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x_arm <= 0;
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y_arm <= 0;
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state <= OBTAIN_DAC_VALUES;
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counter <= 0;
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end
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end
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OBTAIN_DAC_VALUES: begin if (counter < DAC_WAIT_BETWEEN_CMD) begin
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counter <= counter + 1;
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if (!arm) state <= WAIT_ON_ARM;
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end else if (!x_arm || !y_arm) begin
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x_arm <= 1;
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y_arm <= 1;
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end else if (x_finished && y_finished) begin
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x_val <= x_from_dac[DAC_DATA_WID-1:0];
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y_val <= y_from_dac[DAC_DATA_WID-1:0];
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x_arm <= 0;
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y_arm <= 0;
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counter <= 0;
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state <= WAIT_ADVANCE;
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end
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WAIT_ADVANCE: begin
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if (counter < settle_time) begin
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if (!arm) state <= WAIT_ON_ARM;
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counter <= counter + 1;
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end else begin
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adc_arm <= adc_used;
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adc_used_tmp <= adc_used;
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state <= MEASURE;
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end
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end
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MEASURE: begin
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if (adc_finished == adc_arm) begin
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adc_arm <= 0;
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state <= SCAN_ADC_VALUES;
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counter <= 0;
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end
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end
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SCAN_ADC_VALUES: begin
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if (adc_used_tmp == 0) begin
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state <= ON_ADC_FINISHED;
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if (sample == max_samples) begin
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dx <= ~dx + 1;
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dy <= ~dy + 1;
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is_reverse <= !is_reverse;
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sample <= 0;
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if (is_reverse) begin
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state <= NEXT_LINE;
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end else begin
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state <= ADVANCE_DAC_WRITE;
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end
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end else begin
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state <= ADVANCE_DAC_WRITE;
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end
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end else begin
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adc_used_tmp <= adc_used_tmp << 1;
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if (adc_used_tmp[ADCNUM-1]) begin
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state <= SEND_VALUE;
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data <= adc_data_tmp[ADCNUM-1];
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mem_commit <= 1;
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end
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end
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end
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SEND_VALUE: if (mem_finished) begin
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if (!arm) state <= WAIT_ON_ARM;
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state <= SCAN_ADC_VALUES;
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end
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ADVANCE_DAC_WRITE: begin
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if (!x_arm || !y_arm) begin
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x_val <= x_val + dx;
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y_val <= y_val + dy;
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x_to_dac <= {4b'0001, x_val + dx};
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y_to_dac <= {4b'0001, y_val + dy};
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x_arm <= 1;
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y_arm <= 1;
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sample <= sample + 1;
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end else if (x_finished && y_finished) begin
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counter <= 0;
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state <= WAIT_ADVANCE;
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x_arm <= 0;
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y_arm <= 0;
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end
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end
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NEXT_LINE: begin
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if (!x_arm && !y_arm) begin
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if (line == max_lines) begin
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state <= WAIT_ON_ARM_DEASSERT;
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finished <= 1;
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running <= 0;
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end else begin
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x_val <= x_val + dx_vert;
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x_to_dac <= {4b'0001, x_val + dx_vert};
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x_arm <= 1;
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y_val <= y_val + dy_vert;
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y_to_dac <= {4b'0001, y_val + dy_vert};
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y_arm <= 1;
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line <= line + 1;
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end
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end else if (x_finished && y_finished) begin
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counter <= 0;
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state <= WAIT_ADVANCE_LINE;
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x_arm <= 0;
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y_arm <= 0;
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end
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end
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WAIT_ON_ARM_DEASSERT: begin
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if (!arm) begin
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state <= WAIT_ON_ARM;
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finished <= 0;
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end
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end
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endcase
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end
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endmodule
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