diff --git a/doc/verilog_manual.md b/doc/verilog_manual.md
index 74f3575..7ab4c7e 100644
--- a/doc/verilog_manual.md
+++ b/doc/verilog_manual.md
@@ -294,3 +294,11 @@ Another alternative is to use GNU `m4`.
 
 You might have overloaded the CSR bus. Move some CSRs to a wishbone
 bus module. See /gateware/swic.py for some simple Wishbone bus examples.
+This can also happen due to timing errors across the main CPU bus.
+
+## Accesses to a Wishbone bus memory area do not work
+
+Try reading 16 words (64 bytes) into the memory area and see if the
+behavior changes. Many times this is due to the Wishbone Cache interfering
+with volatile memory. Set the `cached` parameter in the SoCRegion to
+`False` when adding the slave.
diff --git a/gateware/rtl/Makefile b/gateware/rtl/Makefile
index 702d664..e0e97ea 100644
--- a/gateware/rtl/Makefile
+++ b/gateware/rtl/Makefile
@@ -3,10 +3,11 @@
 # For license terms, refer to the files in `doc/copying` in the Upsilon
 # source distribution.
 
-all: make_spi
+all:
+	echo "dummy"
 
-make_spi:
-	cd spi && make codegen
+#make_spi:
+#	cd spi && make codegen
 
 
 #make_bram:
diff --git a/gateware/soc.py b/gateware/soc.py
index 0da6a2d..a412606 100644
--- a/gateware/soc.py
+++ b/gateware/soc.py
@@ -167,7 +167,7 @@ class UpsilonSoC(SoCCore):
         pico = PicoRV32(name, origin, origin+0x10)
         self.add_module(name, pico)
         self.bus.add_slave(name + "_dbg_reg", pico.debug_reg_read.bus,
-                SoCRegion(origin=None, size=pico.debug_reg_read.width, cached=True))
+                SoCRegion(origin=None, size=pico.debug_reg_read.width, cached=False))
 
         ram = self.add_blockram(name + "_ram", size=size, connect_now=False)
         ram_iface = self.add_preemptive_interface(name + "ram_iface", 2, ram)
diff --git a/gateware/swic.py b/gateware/swic.py
index 92d0fca..783b9cd 100644
--- a/gateware/swic.py
+++ b/gateware/swic.py
@@ -117,6 +117,7 @@ class ControlLoopParameters(LiteXModule):
                 self.bus.err.eq(0),
         ]
 
+        self.did_write = CSRStatus(8)
         self.sync += [
                 If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
                     Case(self.bus.adr[0:4], {
@@ -125,7 +126,8 @@ class ControlLoopParameters(LiteXModule):
                         0x8: self.bus.dat_r.eq(self.deltaT.storage),
                         0xC: self.bus.dat_r.eq(self.setpt.storage),
                         0x10: If(self.bus.we,
-                                self.zset.status.eq(self.bus.dat_w)
+                                self.zset.status.eq(self.bus.dat_w),
+                                self.did_write.status.eq(self.did_write.status + 1),
                             ).Else(
                                 self.bus.dat_r.eq(self.zset.status)
                             ),
@@ -137,7 +139,7 @@ class ControlLoopParameters(LiteXModule):
                         "default": self.bus.dat_r.eq(0xdeadc0de),
                     }),
                     self.bus.ack.eq(1),
-                ).Elif(self.bus.cyc != 1,
+                ).Elif(~self.bus.cyc,
                     self.bus.ack.eq(0),
                 )
         ]
@@ -146,14 +148,14 @@ class PicoRV32RegisterRead(LiteXModule):
     def __init__(self):
         self.regs = [Signal(32) for i in range(1,32)]
         self.bus = Interface(data_width = 32, address_width = 32, addressing="byte")
-        self.width = 0x80
+        self.width = 0x100
 
         cases = {"default": self.bus.dat_r.eq(0xdeaddead)}
         for i, reg in enumerate(self.regs):
             cases[i*0x4] = self.bus.dat_r.eq(reg)
 
-        # self.debug_addr = CSRStatus(32)
-        # self.debug_cntr = CSRStatus(16)
+        self.debug_addr = CSRStatus(32)
+        self.debug_cntr = CSRStatus(16)
 
         # CYC -> transfer in progress
         # STB -> data is valid on the input lines
@@ -161,8 +163,8 @@ class PicoRV32RegisterRead(LiteXModule):
                 If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
                     Case(self.bus.adr[0:7], cases),
                     self.bus.ack.eq(1),
-                    #self.debug_addr.status.eq(self.bus.adr),
-                    #self.debug_cntr.status.eq(self.debug_cntr.status + 1),
+                    self.debug_addr.status.eq(self.bus.adr),
+                    self.debug_cntr.status.eq(self.debug_cntr.status + 1),
                 ).Elif(self.bus.cyc != 1,
                     self.bus.ack.eq(0)
                 )
diff --git a/swic/load_exec.py b/swic/load_exec.py
index 601f700..b26bd24 100644
--- a/swic/load_exec.py
+++ b/swic/load_exec.py
@@ -17,7 +17,7 @@ def check_running():
     print("Opcode:", u(machine.mem32[pico0_dbg_insn_opcode]))
 
     for num in range(0,31):
-        print("Register", num + 1, u(machine.mem32[pico0_dbg_reg + num*0x4]))
+        print("Reg", num + 1, ":", u(machine.mem32[pico0_dbg_reg + num*0x4]))
 
 def run_program(prog, cl_I):
     # Reset PicoRV32