Documentation and register location generation
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@ -52,6 +52,7 @@ hardware-get:
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docker cp upsilon-hardware:/home/user/upsilon/gateware/soc_subregions.json ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/pico0.json ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/mmio.py ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/pico0_mmio.h ../boot/
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hardware-clean:
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-docker container stop upsilon-hardware
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-docker container rm upsilon-hardware
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@ -34,12 +34,21 @@ The ``machine`` module contains arrays called ``mem8``, ``mem16``, and ``mem32``
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They are used to directly access memory locations on the main CPU bus. Note
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that ``mem32`` accesses must be word aligned.
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Example::
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import machine
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from mmio import *
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machine.mem32[pico0_dbg_reg]
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This reads the first register from ``pico0_dbg_reg``.
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-------------------
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Accessing Registers
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-------------------
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At the lowest level, a program will write to and read from "registers." These
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registers control the operations of various parts of the system.
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At the lowest level, a program will write to and read from "registers" which
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are mapped to memory. These registers control the operations of various parts
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of the system.
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The main bus has two register buses: "CSR" (which is the LiteX default), and
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custom Wishbone code. CSR register information is in the ``csr.json`` file.
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@ -48,6 +57,33 @@ Wishbone bus registers are allocated with regions that are specified in
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``soc_subregions.json``. These should be automatically dumped to the Micropython
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file ``mmio.py`` for easy usage.
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``csr.json`` is not that well documented and can change from version to version
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of LiteX.
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``soc_subregions.json`` is a JSON object where the keys denote ``memories`` in
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``csr.json``. If the object of that key is ``null``, then that region is
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uniform (e.g. it is RAM, which is one continuous block). The objects of each of
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these are registers that reside in the memory region. The keys of the registers
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are
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1. ``origin``: offset of the register from the beginning of the memory.
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2. ``size``: Size of the register in bytes. Right now this is always ``4``,
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even if the writable space is smaller. Always access with words.
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3. ``rw``: True if writable and False if not. Sometimes this is not there
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because the writable might be dynamic or must be inferred from other
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properties.
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4. ``direction``: Specifcally for registers that are Main-write-Pico-read
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or Main-read-Pico-write. ``PR`` denotes Pico-read, ``PW`` denotes Pico-write.
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``pico0.json`` (and other PicoRV32 JSON files) are JSON objects whose keys are
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memory regions. Their values are objects with keys:
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1. ``origin``: Absolute position of the memory region.
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2. ``width``: Width of the memory region in bytes.
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3. ``registers``: Either ``null`` (uniform region, like above), or an object
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whose keys are the names of registers in the region. The values of these
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keys have the same interpretation as ``soc_subregions.json`` above.
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====================
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System Within a Chip
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====================
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@ -58,12 +94,155 @@ programmed and controlled through Micropython.
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The SWiC is a RV32IMC core. Code for the SWiC needs to be compiled for a start
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address of ``0x10000`` and a IRQ handler at ``0x10010``. The default length of
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the SWiC region is ``0x1000`` bytes.
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Each core is given the name ``pico0``, ``pico1``, etc. The regions of each CPU
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are stored in ``pico0.json``, ``pico1.json``, etc. The system used to control
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slave access to the CPU bus is a CSR (and should be in ``mmio.py``).
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----------------------------
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Compiling and Executing Code
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----------------------------
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There is a Makefile in /swic/ that contains the commands to compile a source
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file (with start function ``_start``) to a binary file without static variables
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or RO data.
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Each CPU has a header file (for example ``pico0_mmio.h`` that contains the
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offsets where each word-sized register can be accessed.
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If there is only program code (no RODATA, static variables, etc.) then you can
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dump the ``.text`` section using objdump (this requires a RISC-V compiler
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installed, 64 bit is fine). Afterwards the data can be loaded by writing each
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byte into the RAM section (the start of the ram section in the main CPU
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corresponds to ``0x10000`` on the SWiC).
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More advanced options would require more advanced linker script knowledge.
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----------------
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Complete Example
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----------------
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The compiler can be accessed in the docker container, you can also install it
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under Ubuntu.
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I haven't tested this yet, but this is how the code should work::
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#include "pico0_mmio.h"
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void _start(void) {
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uint32_t i = 0;
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for (;;) {
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*DAC0_TO_SLAVE = i;
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*DAC0_ARM = 1;
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while (*!DAC_FINISHED_OR_READY);
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i += *DAC_FROM_SLAVE;
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*DAC0_ARM = 0;
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}
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}
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This code does reads and writes to registers defined in ``pico0_mmio.h``.
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This file in this example is saved as ``test.c``.
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To compile it use::
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riscv64-unknown-elf-gcc \
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-march=rv32imc \
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-mabi=ilp32 \
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-ffreestanding \
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-nostdlib \
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-Os \
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-Wl,-build-id=none,-Bstatic,-T,riscv.ld,--strip-debug \
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-nostartfiles \
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-lgcc \
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test.c -o test.elf
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In order:
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1. ``-march=rv32imc`` compiles for RISC-V, 32 bit registers, multiplication,
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and compressed instructions.
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2. ``-mabi=ilp32`` compiles for the 32 bit ABI without floating pint.
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3. ``-ffreestanding`` compiles as "Freestanding C" <https://en.cppreference.com/w/c/language/conformance>.
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4. ``-Os`` means "optimize for size."
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5. ``-Wl`` introduces linker commands, I don't know how the linker works.
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6. ``-nostartfiles`` does not include the default ``_start`` in the binary.
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7. ``-lgcc`` links the base GCC library, which is used for builtins (I think).
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8. ``test.c -o test.elf`` compiles the C file and outputs it to ``test.elf``.
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The resulting ELF can be inspected using ``riscv64-unknown-elf-objdump`` (look up
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the instructions). To copy the machine code to ``test.bin``, execute::
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riscv64-unknown-elf-objcopy -O binary -j .text test.elf test.bin
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This code can now be loaded into the PicoRV32's ram. The next code sections
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will be written in Micropython.
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First include the Micropython MMIO locations::
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from mmio import *
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Next import ``machine``. You will almost always need this library.::
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import machine
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Next import the PicoRV32 standard library. (Currently it is hard-coded for pico0,
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this might change if more CPUs are required.)::
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import picorv32
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Next load the code into Micropython::
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with open('test.bin', 'rb') as f:
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prog = f.read()
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This assumes that ``test.bin`` has been uploaded to the FPGA. We now turn off
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the CPU and switch control of the RAM to the main CPU::
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machine.mem32[pico0_enable] = 0
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machine.mem32[pico0ram_iface_master_select] = 0
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Both of these values default to ``0`` on startup.
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Now the program can be loaded into the PicoRV32's ram::
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assert len(prog) < 0xFFF
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for offset, b in enumerate(prog, start=pico0_ram):
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machine.mem8[offset] = b
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The first line of the code makes sure that the code will overflow from the
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RAM region and write other parts of memory. (TODO: this is hardcoded, and
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the size of the region should also be written to memory.)
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The loop goes though each byte of the program and writes it to the RAM,
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starting at the beginning of the RAM. ``enumerate`` is just a fancy Python way
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of a for loop with an increasing counter.
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As a sanity test, check that the program was written correctly::
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for i in range(len(prog)):
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assert machine.mem8[pico_ram + i] == prog[i]
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This can detect overwrite errors (a write to a read-only area will silently
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fail) and cache mismatch errors.
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After the program is loaded, the CPU can finally be started::
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machine.mem32[pico0ram_iface_master_select] = 1
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assert machine.mem8[pico0_ram] == 0
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machine.mem32[pico0_enable] = 1
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The first line switches control of the RAM to the PicoRV32. The second line
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checks if the switch worked. If this line fails, most likely the preemptive
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interface is not properly connected to the PicoRV32 (or my code is buggy).
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The final line starts the CPU.
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The state of the CPU can be inspected using ``picorv32.dump()``. This will
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tell you if the CPU is in a trap state and what registers the CPU is currently
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reading.
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================
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Computer Control
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================
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@ -71,8 +250,7 @@ Computer Control
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Micropython code can be loaded manually with SSH but this gets cumbersome.
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Python scripts on the controlling computer connected to the Upsilon FPGA can
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upload, execute, and read data back from the FPGA automatically. The code that
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does this is in /client/ . This will be updated because of the recent structural
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changes to Upsilon.
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does this is in /client/ . They don't work right now and need to be updated.
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===
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FAQ
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@ -85,6 +85,11 @@ You must also change the port in `upsilon/build/Makefile` under `tftp`.
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Run `make images` to create all docker images.
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## Copy Default Config
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If you do not have a ``config.py`` file in ``/gateware``, copy ``config.py.def``
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to ``config.py``.
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## Setup and Run Containers
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For `NAME` in `hardware`, `opensbi`, `buildroot`:
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@ -108,19 +108,40 @@ The only masters and slaves that are word-addressed are the ones that are
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from LiteX itself. Those have special code to convert to the byte-addressed
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masters/slaves.
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If the slave has one bus, it **must** be an attribute called ``bus``.
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Each class that is accessed by a wishbone bus **must** have an attribute
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called ``width`` that is the size, in bytes, of the region. This must be a power
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of 2 (exception: wrappers around slaves since they might wrap LiteX slaves
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that don't have ``width`` attributes).
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Each class **should** have a attribute ``public_registers`` that is a dictionary,
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keys are names of the register shown to the programmer and
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1. ``origin``: offset of the register in memory
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2. ``size``: size of the register in bytes (multiple of 4)
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are required attributes. Other attributes are ``rw``, ``direction``, that are
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explained in /doc/controller_manual.rst .
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-----------------------------
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Adding Slaves to the Main CPU
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-----------------------------
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After adding a module with an ``Interface``, the interface is connected to
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to main CPU bus by adding::
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to main CPU bus by calling one of two functions.
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self.add_slave(name, iface, SoCRegion(origin=None, size=iface.width, cached=False)
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If the slave region has no special areas in it, call::
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self.bus.add_slave(name, slave.bus, SoCRegion(origin=None, size=slave.width, cached=False)
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If the slave region has registers, add::
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self.add_slave_with_registers(name, iface, SoCRegion(...), slave.public_registers)
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where the SoCRegion parameters are the same as before. Each slave device
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should have a ``slave.width`` and a ``slave.public_registers`` attribute,
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unless noted. Some slaves have only one bus, some have multiple.
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The Wishbone cache is very confusing and causes custom Wishbone bus code to
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not work properly. Since a lot of this memory is volatile you should never
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@ -10,13 +10,23 @@ DEVICETREE_GEN_DIR=.
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all: build/digilent_arty/digilent_arty.bit arty.dtb mmio.py
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csr.json build/digilent_arty/digilent_arty.bit: soc.py
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mmio.py csr.json build/digilent_arty/digilent_arty.bit: soc.py
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@# Litex Version Check (current version 2023.12)
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@if ! pip show litex | awk '/Version:/ { split($$2, a, "\\."); if (a[1] < 2023 || a[2] < 12) exit(1)}'; then \
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pip show litex; \
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echo "You are using an old version of LiteX!"; \
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echo "Update LiteX or remake your image."; \
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exit 1; \
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fi
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@if [ ! -f config.py ]; then \
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echo "No config file found! If you are just starting, do"; \
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echo "$$ cp config.py.def config.py"; \
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fi
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cd rtl && make
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python3 soc.py
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mmio.py: csr.json csr2mp.py
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python3 csr2mp.py > mmio.py
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clean:
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rm -rf build csr.json arty.dts arty.dtb mmio.py
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@ -1,34 +0,0 @@
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#!/usr/bin/python3
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# Copyright 2023 (C) Peter McGoron
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#
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# This file is a part of Upsilon, a free and open source software project.
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# For license terms, refer to the files in `doc/copying` in the Upsilon
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# source distribution.
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#######################################################################
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#
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# This file generates memory locations
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#
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# TODO: Devicetree?
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import collections
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import argparse
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import json
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with open('csr.json', 'rt') as f:
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csrs = json.load(f)
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print("from micropython import const")
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for key in csrs["csr_registers"]:
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if key.startswith("pico0"):
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print(f'{key} = const({csrs["csr_registers"][key]["addr"]})')
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with open('soc_subregions.json', 'rt') as f:
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subregions = json.load(f)
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for key in subregions:
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if subregions[key] is None:
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print(f'{key} = const({csrs["memories"][key]["base"]})')
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else:
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print(f'{key}_base = const({csrs["memorys"][key]["base"]})')
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print(f'{key} = {subregions[key].__repr__()}')
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@ -30,7 +30,7 @@ class SPIMaster(Module):
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width = 0x10
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registers = {
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public_registers = {
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"finished_or_ready": {
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"origin" : 0,
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"width" : 4,
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@ -61,7 +61,7 @@ class BasicRegion:
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return lambda addr: addr[rightbits:32] == (self.origin >> rightbits)
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def to_dict(self):
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return {"origin" : self.origin, "size": self.size, "registers": self.registers}
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return {"origin" : self.origin, "width": self.size, "registers": self.registers}
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def __str__(self):
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return str(self.to_dict())
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@ -64,6 +64,7 @@ from util import *
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from swic import *
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from extio import *
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from region import BasicRegion
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import json
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"""
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Keep this diagram up to date! This is the wiring diagram from the ADC to
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@ -150,14 +151,29 @@ class _CRG(Module):
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class UpsilonSoC(SoCCore):
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def add_ip(self, ip_str, ip_name):
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# The IP of the FPGA and the IP of the TFTP server are stored as
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# "constants" which turn into preprocessor defines.
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# They are IPv4 addresses that are split into octets. So the local
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# ip is LOCALIP1, LOCALIP2, etc.
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for seg_num, ip_byte in enumerate(ip_str.split('.'),start=1):
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self.add_constant(f"{ip_name}{seg_num}", int(ip_byte))
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def add_slave_with_registers(self, name, bus, region, registers):
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""" Add a bus slave, and also add its registers to the subregions
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dictionary. """
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self.bus.add_slave(name, bus, region)
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self.soc_subregions[name] = registers
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def add_blockram(self, name, size, connect_now=True):
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""" Add a blockram module to the system.
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:param connect_now: Connect the block ram directly to the SoC.
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You will probably never need this, since this just adds
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more ram to the main CPU which already has 256 MiB of RAM.
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Only useful for testing to see if the Blockram works by poking
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it directly from the main CPU.
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"""
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mod = SRAM(size)
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self.add_module(name, mod)
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@ -167,31 +183,48 @@ class UpsilonSoC(SoCCore):
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return mod
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def add_preemptive_interface(self, name, size, slave):
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""" Add a preemptive interface with "size" connected to the slave's bus. """
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mod = PreemptiveInterface(size, slave)
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self.add_module(name, mod)
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return mod
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def add_picorv32(self, name, size=0x1000, origin=0x10000):
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# Add PicoRV32 core
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pico = PicoRV32(name, origin, origin+0x10)
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self.add_module(name, pico)
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# Attach the register region to the main CPU.
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self.add_slave_with_registers(name + "_dbg_reg", pico.debug_reg_read.bus,
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SoCRegion(origin=None, size=pico.debug_reg_read.width, cached=False),
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pico.debug_reg_read.registers)
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pico.debug_reg_read.public_registers)
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# Add a Block RAM for the PicoRV32 toexecute from.
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ram = self.add_blockram(name + "_ram", size=size, connect_now=False)
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# Control access to the Block RAM from the main CPU.
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ram_iface = self.add_preemptive_interface(name + "ram_iface", 2, ram)
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# Allow access from the PicoRV32 to the Block RAM.
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pico.mmap.add_region("main",
|
||||
BasicRegion(origin=origin, size=size, bus=ram_iface.buses[1]))
|
||||
|
||||
# Allow access from the main CPU to the Block RAM.
|
||||
self.add_slave_with_registers(name + "_ram", ram_iface.buses[0],
|
||||
SoCRegion(origin=None, size=size, cached=True),
|
||||
None)
|
||||
|
||||
def picorv32_add_cl(self, name, param_origin=0x100000):
|
||||
""" Add a register area containing the control loop parameters to the
|
||||
PicoRV32.
|
||||
|
||||
:param param_origin: The origin of the parameters in the PicoRV32's
|
||||
address space. """
|
||||
pico = self.get_module(name)
|
||||
param_iface = pico.add_cl_params(param_origin, name + "_cl.json")
|
||||
self.bus.add_slave(name + "_cl", param_iface,
|
||||
SoCRegion(origin=None, size=size, cached=False))
|
||||
params = pico.add_cl_params(param_origin, name + "_cl.json")
|
||||
self.add_slave_with_registers(name + "_cl", params.mainbus,
|
||||
SoCRegion(origin=None, size=params.width, cached=False),
|
||||
params.public_registers)
|
||||
|
||||
def add_AD5791(self, name, **kwargs):
|
||||
args = SPIMaster.AD5791_PARAMS
|
||||
|
|
@ -304,8 +337,10 @@ class UpsilonSoC(SoCCore):
|
|||
|
||||
# Add control loop DACs and ADCs.
|
||||
self.add_picorv32("pico0")
|
||||
self.picorv32_add_cl("pico0")
|
||||
# XXX: I don't have the time to restructure my code to make it
|
||||
# elegant, that comes when things work
|
||||
# If DACs don't work, comment out from here
|
||||
module_reset = platform.request("module_reset")
|
||||
self.add_AD5791("dac0",
|
||||
rst=module_reset,
|
||||
|
|
@ -318,11 +353,11 @@ class UpsilonSoC(SoCCore):
|
|||
self.add_preemptive_interface("dac0_PI", 2, self.dac0)
|
||||
self.add_slave_with_registers("dac0", self.dac0_PI.buses[0],
|
||||
SoCRegion(origin=None, size=self.dac0.width, cached=False),
|
||||
self.dac0.registers)
|
||||
self.dac0.public_registers)
|
||||
self.pico0.mmap.add_region("dac0",
|
||||
BasicRegion(origin=0x200000, size=self.dac0.width,
|
||||
bus=self.dac0_PI.buses[1],
|
||||
registers=self.dac0.registers))
|
||||
registers=self.dac0.public_registers))
|
||||
|
||||
self.add_LT_adc("adc0",
|
||||
rst=module_reset,
|
||||
|
|
@ -334,22 +369,46 @@ class UpsilonSoC(SoCCore):
|
|||
self.add_preemptive_interface("adc0_PI", 2, self.adc0)
|
||||
self.add_slave_with_registers("adc0", self.adc0_PI.buses[0],
|
||||
SoCRegion(origin=None, size=self.adc0.width, cached=False),
|
||||
self.adc0.registers)
|
||||
self.adc0.public_registers)
|
||||
self.pico0.mmap.add_region("adc0",
|
||||
BasicRegion(origin=0x300000, size=self.adc0.width,
|
||||
bus=self.adc0_PI.buses[1],
|
||||
registers=self.adc0.registers))
|
||||
registers=self.adc0.public_registers))
|
||||
# To here
|
||||
|
||||
def do_finalize(self):
|
||||
with open('soc_subregions.json', 'wt') as f:
|
||||
import json
|
||||
json.dump(self.soc_subregions, f)
|
||||
|
||||
def generate_main_cpu_include(csr_file):
|
||||
""" Generate Micropython include from a JSON file. """
|
||||
with open('mmio.py', 'wt') as out:
|
||||
|
||||
print("from micropython import const", file=out)
|
||||
with open(csr_file, 'rt') as f:
|
||||
csrs = json.load(f)
|
||||
|
||||
for key in csrs["csr_registers"]:
|
||||
if key.startswith("pico0"):
|
||||
print(f'{key} = const({csrs["csr_registers"][key]["addr"]})', file=out)
|
||||
|
||||
with open('soc_subregions.json', 'rt') as f:
|
||||
subregions = json.load(f)
|
||||
|
||||
for key in subregions:
|
||||
if subregions[key] is None:
|
||||
print(f'{key} = const({csrs["memories"][key]["base"]})', file=out)
|
||||
else:
|
||||
print(f'{key}_base = const({csrs["memories"][key]["base"]})', file=out)
|
||||
print(f'{key} = {subregions[key].__repr__()}', file=out)
|
||||
|
||||
def main():
|
||||
from config import config
|
||||
soc =UpsilonSoC(**config)
|
||||
builder = Builder(soc, csr_json="csr.json", compile_software=True)
|
||||
builder.build()
|
||||
|
||||
generate_main_cpu_include("csr.json")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
|
|
@ -4,6 +4,9 @@
|
|||
# For license terms, refer to the files in `doc/copying` in the Upsilon
|
||||
# source distribution.
|
||||
|
||||
# XXX: PicoRV32 code only handles word-sized registers correctly. Memory
|
||||
# regions made up of multiple words are not supported right now.
|
||||
|
||||
from migen import *
|
||||
from litex.soc.interconnect.csr import CSRStorage, CSRStatus
|
||||
from litex.soc.interconnect.wishbone import Interface, SRAM, Decoder
|
||||
|
|
@ -183,8 +186,8 @@ class RegisterInterface(LiteXModule):
|
|||
bus_logic(self.picobus, pico_case)
|
||||
|
||||
# Generate addresses
|
||||
self.addresses = {}
|
||||
for reg, off in self.registers:
|
||||
self.public_registers = {}
|
||||
for reg, off in self.public_registers:
|
||||
self.addresses[reg.name] = {
|
||||
"width" : reg.width,
|
||||
"direction" : reg.direction,
|
||||
|
|
@ -197,7 +200,7 @@ class RegisterRead(LiteXModule):
|
|||
"s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2",
|
||||
"s3", "s4", "s5", "s6", "s7", "t3", "t4", "t5", "t6",
|
||||
}
|
||||
registers = {name: {"origin" : num * 4, "size" : 4, "rw": False} for num, name in enumerate(pico_registers)}
|
||||
public_registers = {name: {"origin" : num * 4, "width" : 4, "rw": False} for num, name in enumerate(pico_registers)}
|
||||
""" Inspect PicoRV32 registers via Wishbone bus. """
|
||||
def __init__(self):
|
||||
self.regs = [Signal(32) for i in range(1,32)]
|
||||
|
|
@ -219,6 +222,24 @@ class RegisterRead(LiteXModule):
|
|||
)
|
||||
]
|
||||
|
||||
def gen_pico_header(pico_name):
|
||||
""" Generate PicoRV32 C header for this CPU from JSON file. """
|
||||
import json
|
||||
with open(pico_name + "_mmio.h", "wt") as out:
|
||||
print('#pragma once', file=out)
|
||||
|
||||
with open(pico_name + ".json") as f:
|
||||
js = json.load(f)
|
||||
|
||||
for region in js:
|
||||
if js[region]["registers"] is None:
|
||||
continue
|
||||
origin = js[region]["origin"]
|
||||
for reg in js[region]["registers"]:
|
||||
macname = f"{region}_{reg}".upper()
|
||||
loc = origin + js[region]["registers"][reg]["origin"]
|
||||
print(f"#define {macname} (volatile uint32_t *)({loc})", file=out)
|
||||
|
||||
# Parts of this class come from LiteX.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
|
|
@ -247,8 +268,7 @@ class PicoRV32(LiteXModule):
|
|||
("zpos", "PW", 32),
|
||||
))
|
||||
self.add_module("cl_params", params)
|
||||
self.mmap.add_region("cl_params", BasicRegion(origin, params.width, params.picobus, params.addresses))
|
||||
params.dump_json(dumpname)
|
||||
self.mmap.add_region("cl_params", BasicRegion(origin, params.width, params.picobus, params.public_registers))
|
||||
return params
|
||||
|
||||
def __init__(self, name, start_addr=0x10000, irq_addr=0x10010, stackaddr=0x100FF):
|
||||
|
|
@ -344,4 +364,5 @@ class PicoRV32(LiteXModule):
|
|||
|
||||
def do_finalize(self):
|
||||
self.mmap.dump_mmap(self.name + ".json")
|
||||
gen_pico_header(self.name)
|
||||
self.mmap.finalize()
|
||||
|
|
|
|||
|
|
@ -21,6 +21,9 @@ def u(n):
|
|||
# Converts possibly signed number to unsigned 32 bit.
|
||||
return hex(n & 0xFFFFFFFF)
|
||||
|
||||
|
||||
# XXX: Currently hardcoded for Pico0. Future versions should accept a
|
||||
# class that has fields.
|
||||
def dump():
|
||||
print("Running:", "yes" if machine.mem32[pico0_enable] else "no")
|
||||
print("Trap status:", trapcode[machine.mem32[pico0_trap]])
|
||||
|
|
|
|||
Loading…
Reference in New Issue