checks and misc fix
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5287366140
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75e1001452
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@ -23,7 +23,7 @@ enum adc_types {
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};
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uint32_t
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adc_read(int num, enum adc_types ty)
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adc_read(size_t num, enum adc_types ty)
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{
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uint32_t r = 0;
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// TODO
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@ -37,7 +37,7 @@ adc_read(int num, enum adc_types ty)
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LOG_ERROR("adc_read got unknown ADC type\n");
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k_fatal_halt(K_ERR_KERNEL_OOPS);
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}
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if (num < 0 || num >= ADC_MAX) {
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if (num >= ADC_MAX) {
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LOG_ERROR("Bad ADC %d\n", num);
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k_fatal_halt(K_ERR_KERNEL_OOPS);
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}
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@ -45,7 +45,7 @@ adc_read(int num, enum adc_types ty)
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*adc_sck[num] = 0;
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*adc_conv[num] = 1;
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k_sleep(K_NSEC(T_CONV + T_DSOBUSYL));
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k_sleep(K_NSEC(time[ty].conv_time));
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*adc_conv[num] = 0;
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for (int i = 0; i < time[ty].wid; i++) {
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@ -56,6 +56,7 @@ adc_read(int num, enum adc_types ty)
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/* 1 millisecond -> 1 MHz */
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k_sleep(K_NSEC(500));
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*adc_sck[num] = 0;
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k_sleep(K_NSEC(500));
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}
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return r;
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@ -75,13 +76,18 @@ adc_read(int num, enum adc_types ty)
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* 5) Set SCK high, wait setup time.
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*/
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uint32_t
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dac_write_raw(int n, uint32_t data)
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dac_write_raw(size_t n, uint32_t data)
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{
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uint32_t r = 0;
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DAC_SCK(n, 1);
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DAC_SS(n, 1);
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k_sleep(K_NSEC(10));
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if (n >= DAC_MAX) {
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LOG_ERROR("dac_write_raw got bad ADC %d\n", n);
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k_fatal_halt(K_ERR_KERNEL_OOPS);
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}
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for (int i = 0; i < 20; i++) {
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DAC_SCK(n, 0);
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DAC_MOSI(n, data >> 31 & 1);
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@ -98,13 +104,13 @@ dac_write_raw(int n, uint32_t data)
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}
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void
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dac_write_v(int n, uint32_t v)
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dac_write_v(size_t n, uint32_t v)
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{
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dac_write_raw(n, (1 << 20) | (v & 0xFFFFF));
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}
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int
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dac_init(int n)
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dac_init(size_t n)
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{
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/* Write to control register. */
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const uint32_t msg =
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