diff --git a/firmware/rtl/control_loop/intro.md b/firmware/rtl/control_loop/intro.md
index 5b18e72..c1e9bc5 100644
--- a/firmware/rtl/control_loop/intro.md
+++ b/firmware/rtl/control_loop/intro.md
@@ -28,7 +28,8 @@ cycle, which in turn requires knowing the ADC and DAC timings.  This
 is done outside the Verilog code.  and can be calculated from
 simulating one iteration of the control loop.
 
-************** Fixed Point Integers************
+# Fixed Point Integers
+
 A regular number is stored in decimal: 123056.
 This is equal to