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@ -123,7 +123,9 @@ hardware that is executing the scan.
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LiteX further uses F4PGA to compile the HDL code. F4PGA is primarily
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made up of Yosys (synthesis) and nextpnr (place and route).
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# Setting up the Toolchain
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# Compile Process
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## Setting up the Toolchain
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The toolchain is primarily designed around modern Linux. It may not work
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properly on Windows or MacOS. If you have access to a computational
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@ -131,7 +133,115 @@ cluster (if you are at FSU physics, ask the Physics department) then
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you should set up the toolchain on their servers. You will be able to
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compile things on any computer with an internet connection.
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TODO
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### F4PGA
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1. Clone [F4PGA](https://github.com/chipsalliance/f4pga) (if you want,
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checkout commit `b6c5fff`, but you should try checking out master
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first)
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2. Run `scripts/prepare_environment.sh`. Note that you will need to change
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the environment variable `$F4PGA_INSTALL_DIR` if you do not have access
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to the default directory (which is root access).
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3. Run `scripts/activate.sh`. If you run into problems, open the file and
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copy the `source` and `conda` commands manually into your terminal.
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4. Install meson and ninja through pip.
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All commands should be done in the conda environment.
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### Zephyr OS
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These instructions are based on [these][zephyr_getting_started], but the Zephyr
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environment should be installed into the F4PGA conda environment,
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[zephyr_getting_started]: https://docs.zephyrproject.org/latest/develop/getting_started/index.html
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1. Run `pip3 install west`
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2. Run
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```
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west init $ZEPHYR_DIRECTORY/zephyrproject
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cd $ZEPHYR_DIRECTORY/zephyrproject
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west update
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west zephyr-export
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pip install -r ~/zephyrproject/zephyr/scripts/requirements.txt
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cd $ZEPHYR_DIRECTORY/zephyrproject
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wget https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.16.0/zephyr-sdk-0.16.0_linux-x86_64.tar.xz
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wget -O - https://github.com/zephyrproject-rtos/sdk-ng/releases/download/v0.16.0/sha256.sum | shasum --check --ignore-missing
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tar xvf zephyr-sdk-0.16.0_linux-x86_64.tar.xz
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cd zephyr-sdk-0.16.0
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./setup.sh
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```
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### LiteX
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1. Download `litex_setup.py` from the [LiteX repository][litex_repo], Upsilon
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uses 2022.08 to some directory (don't put it in your home directory because
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there will be a bunch of downloaded repositories.
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2. Run `litex_setup.py --init --install --user --tag 2022.08`
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3. Download a GCC RISC-V cross compiler. If you have root access to the build
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machine, then you can probably install this with your package manager. Users
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of Ubuntu 14 can download the [sifive][sifive_gcc] GCC. Otherwise you will have
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to compile a cross compiler (`x86_64` host to RV32I target) manually.
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4. Put the GCC RISC-V cross compiler in your `$PATH` variable.
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[litex_repo]: https://github.com/enjoy-digital/litex
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[sifive_gcc]: https://github.com/sifive/freedom-tools/releases
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## FPGA Build System
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Make sure F4PGA and a RISC-V GCC compiler are in your path. Then just go into
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the `firmware` folder and run `make`. This should generate everything you need
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and compile the software. The synthesis suite is single threaded. This will
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take about 15-20 minutes on a good computer.
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The FPGA firmware (aka gateware) build system is designed in a recursive
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manner. That means that each directory has a Makefile that processes all the
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files in the directory. There is a `common.makefile` in the `rtl/` directory
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that is used when a rule (such as preprocessing a Verilog source file)
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is used in multiple Makefiles.
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For the Arty A7, the bitstream is `firmware/build/digilent_arty/gateware/digilent_arty.bit`.
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## Software Build System
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This requires at least CMake 3.20.0 (you can install this using `conda`).
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Afterwards just run `make` and everything should work. Everything is
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managed by the `CMakeLists.txt` and the `prj.conf`, see the Zephyr OS
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documentation.
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The kernel is `/software/build/zephyr/zephyr.bin`
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# Loading the Software and Firmware
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## Network Setup
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You will need the FPGA and the controlling computer on the same wired
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network. **DO NOT CONNECT THE FPGA TO A WIDE NETWORK. USE A PRIVATE LAN
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THAT ONLY CONTAINS THE CONTROLLING COMPUTER AND THE FPGA. DO NOT ATTEMPT
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TO CONNECT THE FPGA TO THE INTERNET.** The controlling computer can
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still connect to the internet, but through another LAN port. The best
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thing to do is to buy a USB to Ethernet adapter.
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You will need some way to do DHCP. The best way is to use a router, but
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a standard wireless router will not fly with any IT department because
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of the security risk. You need to find a non-wireless router (like a
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managed switch). You can even retrofit an old computer into a router
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(just needs another ethernet port).
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The default TFTP client connects to 192.168.1.50.
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## Loading the Firmware
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Connect the FPGA to a computer using a Micro-USB to USB cable. Run
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`openFPGALoader -c digilent digilent_arty.bit` to upload the firmware
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(gateware) to the controller.
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You can load the software using serial boot but this is very slow. The
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better thing to do is to use TFTP boot, which goes over Ethernet.
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**WHEN YOU RUN TFTP, DO NOT EXPOSE YOUR INTERFACE TO THE INTERNET
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CONNECTED NETWORK INTERFACE. THIS IS A BIG SECURITY RISK. ONLY RUN
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TFTP FOR THE AMOUNT OF TIME REQUIRED TO BOOT THE CONTROL SOFTWARE.**
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You can read about how to setup a TFTP server on the [OpenWRT wiki][owrt_wiki].
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[owrt_wiki]: https://openwrt.org/docs/guide-user/troubleshooting/tftpserver
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# Design Testing Process
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@ -301,7 +411,7 @@ write big Creole programs.
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# Hacks and Pitfalls
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The open source toolchain that Upsilon uses is novel and unstable.
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The open source software stack that Upsilon uses is novel and unstable.
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## F4PGA
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@ -333,3 +443,37 @@ Verilator. For example, if you have a file called `mod.v` in the folder
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(putting it after all other generated files). The file
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`firmware/rtl/common.makefile` should automatically generate the
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preprocessed file for you.
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## If The Controlling Computer Cannot Connect to the Internet
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When you connect your computer to the controller over Ethernet, your computer
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may attempt to route all traffic over the controller network (since it is
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wired) instead of another network (like a wireless network). This means that
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your computer can't connect to the internet (or your connection is really slow).
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If this happens to you on a Linux machine, you can change the routing table.
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Run `route -n` (or `ip route` if this does not work) to print the routing table.
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Find the entry named `default via [...] dev eth-interface`. This is the default route
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for the ethernet device. Remove it using `ip route del default via [...] dev eth-interface`.
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If the route keeps on reappearing, delete it and quickly enter
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`ip route del default via [...] dev eth0 metric 65534`. This will make the
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route the last priority.
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## Getting The Correct IP for the Controlling Computer
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Some routers can automatically assign IPs based on MAC address. If your computer
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can do that, great. Otherwise you will need to configure your computer with a
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static ip.
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1. Remove your computer from the DHCP list that the router has.
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2. Run `ip link set eth-interface down`.
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3. Then run `ip addr` and run `ip addr remove del [ip] dev eth-interface` on
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each ip on the ethernet interface that is connected to the controller.
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3. Run `ip addr add 192.168.1.100/24 dev eth-interface` (or whatever ip + subnet
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mask you need)
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4. Run `ip route add 192.168.1.0/24 dev eth0 proto kernel scope link` (again,
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change depending on different situations)
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This will use the static ip `192.168.1.100`, which is the default TFTP boot
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IP.
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self.submodules.base = Base(ClockSignal(), self.sdram, platform)
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def main():
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soc = CryoSNOM1SoC("a7-35")
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builder = Builder(soc, csr_json="csr.json", compile_software=False)
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soc = CryoSNOM1SoC("a7-100")
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builder = Builder(soc, csr_json="csr.json", compile_software=True)
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builder.build()
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if __name__ == "__main__":
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