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(somewhat) fix counter

This commit is contained in:
Peter McGoron 2022-11-21 22:08:25 -05:00
parent cfb0f92528
commit 79cae3dd66
1 changed files with 2 additions and 1 deletions
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3
firmware/rtl/control_loop/control_loop.v
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@ -229,7 +229,7 @@ always @ (posedge clk) begin
if (state == CYCLE_START && timer == 0) begin if (state == CYCLE_START && timer == 0) begin
counting_timer <= 1; counting_timer <= 1;
last_timer <= counting_timer; last_timer <= counting_timer;
end else begin end else if (running) begin
counting_timer <= counting_timer + 1; counting_timer <= counting_timer + 1;
end end
end end
@ -353,6 +353,7 @@ always @ (posedge clk) begin
state <= CYCLE_START; state <= CYCLE_START;
dac_ss <= 0; dac_ss <= 0;
dac_arm <= 0; dac_arm <= 0;
timer <= 0;
stored_dac_val <= from_dac[DAC_DATA_WID-1:0]; stored_dac_val <= from_dac[DAC_DATA_WID-1:0];
end end
end end