(somewhat) fix counter
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cfb0f92528
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@ -229,7 +229,7 @@ always @ (posedge clk) begin
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if (state == CYCLE_START && timer == 0) begin
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if (state == CYCLE_START && timer == 0) begin
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counting_timer <= 1;
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counting_timer <= 1;
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last_timer <= counting_timer;
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last_timer <= counting_timer;
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end else begin
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end else if (running) begin
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counting_timer <= counting_timer + 1;
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counting_timer <= counting_timer + 1;
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end
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end
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end
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end
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@ -353,6 +353,7 @@ always @ (posedge clk) begin
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state <= CYCLE_START;
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state <= CYCLE_START;
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dac_ss <= 0;
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dac_ss <= 0;
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dac_arm <= 0;
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dac_arm <= 0;
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timer <= 0;
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stored_dac_val <= from_dac[DAC_DATA_WID-1:0];
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stored_dac_val <= from_dac[DAC_DATA_WID-1:0];
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end
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end
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end
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end
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