From 93c92b9f554eb5f4a7ae88e45f402ebf8afbc295 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Mon, 20 Mar 2023 13:57:15 -0400 Subject: [PATCH 1/4] add test scripts for synthesizing ram fifo --- firmware/rtl/raster/flow.json | 24 ++++++++++++++++++++++++ firmware/rtl/raster/script | 4 ++++ firmware/rtl/raster/synth_test_top.v | 28 ++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 firmware/rtl/raster/flow.json create mode 100644 firmware/rtl/raster/script create mode 100644 firmware/rtl/raster/synth_test_top.v diff --git a/firmware/rtl/raster/flow.json b/firmware/rtl/raster/flow.json new file mode 100644 index 0000000..7034f6b --- /dev/null +++ b/firmware/rtl/raster/flow.json @@ -0,0 +1,24 @@ +{ + "default_part": "XC7A35TCSG324-1", + "values": { + "top": "top" + }, + "dependencies": { + "sources": [ + "synth_test_top.v", + "ram_fifo_dual_port.v", + "ram_fifo.v" + ], + "synth_log": "synth.log", + "pack_log": "pack.log" + }, + "XC7A35TCSG324-1": { + "default_target": "bitstream", + "dependencies": { + "build_dir": "build/arty_35", + "xdc": [ + "arty.xdc" + ] + } + } +} diff --git a/firmware/rtl/raster/script b/firmware/rtl/raster/script new file mode 100644 index 0000000..6714108 --- /dev/null +++ b/firmware/rtl/raster/script @@ -0,0 +1,4 @@ +read_verilog raster.v +synth_xilinx -flatten -nosrl -noclkbuf -nodsp -iopad -nowidelut +# synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut +write_verilog synth_test_yosys.v diff --git a/firmware/rtl/raster/synth_test_top.v b/firmware/rtl/raster/synth_test_top.v new file mode 100644 index 0000000..0cf97f9 --- /dev/null +++ b/firmware/rtl/raster/synth_test_top.v @@ -0,0 +1,28 @@ +module top ( + input clk, + input [1:0] btn, + input ck_io0, + input ck_io1, + input ck_io2, + input ck_io3, + output ck_io4, + output ck_io5, + output ck_io6, + output ck_io7, +); + + wire bufg; + BUFG bufgctrl ( + .I(clk), + .O(bufg) + ); + + ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf ( + .clk(bufg), + .rst(0), + .read_enable(btn[0]), + .write_enable(btn[1]), + .write_dat({ck_io0,ck_io1,ck_io2,ck_io3}), + .read_dat({ck_io4,ck_io5,ck_io6,ck_io7}) + ); +endmodule From 0259523d201904875cfdcb49c39fc1eb783fe7ab Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Mon, 20 Mar 2023 13:57:42 -0400 Subject: [PATCH 2/4] add yosys synth test for control loop --- firmware/rtl/control_loop/yosys_test.sh | 1 + 1 file changed, 1 insertion(+) create mode 100644 firmware/rtl/control_loop/yosys_test.sh diff --git a/firmware/rtl/control_loop/yosys_test.sh b/firmware/rtl/control_loop/yosys_test.sh new file mode 100644 index 0000000..a983d3c --- /dev/null +++ b/firmware/rtl/control_loop/yosys_test.sh @@ -0,0 +1 @@ +yosys -p "plugin -i systemverilog" -p "read_systemverilog control_loop.v control_loop_math.v ../spi/spi_master_ss_no_write.v ../spi/spi_master_ss.v boothmul.v intsat.v ../spi/spi_master.v ../spi/spi_master_no_write.v" -p "synth_xilinx" From f90348aff95267b27fc1fd0d3c484a703e836b88 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Mon, 20 Mar 2023 13:58:35 -0400 Subject: [PATCH 3/4] arty.xdc for synth test --- firmware/rtl/raster/arty.xdc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 firmware/rtl/raster/arty.xdc diff --git a/firmware/rtl/raster/arty.xdc b/firmware/rtl/raster/arty.xdc new file mode 100644 index 0000000..07bc67e --- /dev/null +++ b/firmware/rtl/raster/arty.xdc @@ -0,0 +1,17 @@ +# Clock pin +set_property PACKAGE_PIN E3 [get_ports {clk}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk}] + +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2] +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3] +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] + +# Clock constraints +create_clock -period 10.0 [get_ports {clk}] From a55c791adda6bd0dd188414f74cc81f7c4dda195 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Mon, 20 Mar 2023 13:59:01 -0400 Subject: [PATCH 4/4] .gitignore --- .gitignore | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/.gitignore b/.gitignore index 731b7d6..ccd5e19 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,14 @@ firmware/rtl/control_loop/control_loop.v firmware/rtl/control_loop/control_loop_cmds.vh firmware/rtl/control_loop/control_loop_math.v *_preprocessed.v +firmware/csr.repl +firmware/csr.resc +firmware/rtl/control_loop/slpp_all/ +firmware/rtl/raster/.f4cache +firmware/rtl/raster/build/ +firmware/rtl/raster/pack.log +firmware/rtl/raster/place.log +firmware/rtl/raster/route.log +firmware/rtl/raster/synth.log +firmware/rtl/raster/synth_test_yosys.v +firmware/rtl/raster/yosys_output