add test scripts for synthesizing ram fifo
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{
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"default_part": "XC7A35TCSG324-1",
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"values": {
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"top": "top"
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},
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"dependencies": {
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"sources": [
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"synth_test_top.v",
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"ram_fifo_dual_port.v",
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"ram_fifo.v"
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],
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"synth_log": "synth.log",
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"pack_log": "pack.log"
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},
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"XC7A35TCSG324-1": {
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"default_target": "bitstream",
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"dependencies": {
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"build_dir": "build/arty_35",
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"xdc": [
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"arty.xdc"
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]
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}
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}
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}
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read_verilog raster.v
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synth_xilinx -flatten -nosrl -noclkbuf -nodsp -iopad -nowidelut
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# synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut
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write_verilog synth_test_yosys.v
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module top (
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input clk,
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input [1:0] btn,
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input ck_io0,
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input ck_io1,
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input ck_io2,
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input ck_io3,
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output ck_io4,
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output ck_io5,
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output ck_io6,
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output ck_io7,
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);
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wire bufg;
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BUFG bufgctrl (
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.I(clk),
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.O(bufg)
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);
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ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf (
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.clk(bufg),
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.rst(0),
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.read_enable(btn[0]),
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.write_enable(btn[1]),
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.write_dat({ck_io0,ck_io1,ck_io2,ck_io3}),
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.read_dat({ck_io4,ck_io5,ck_io6,ck_io7})
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);
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endmodule
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