add test scripts for synthesizing ram fifo

firmware/rtl/raster/flow.json

@@ -0,0 +1,24 @@
+{
+    "default_part": "XC7A35TCSG324-1",
+    "values": {
+        "top": "top"
+    },
+    "dependencies": {
+        "sources": [
+            "synth_test_top.v",
+	    "ram_fifo_dual_port.v",
+	    "ram_fifo.v"
+        ],
+        "synth_log": "synth.log",
+        "pack_log": "pack.log"
+    },
+    "XC7A35TCSG324-1": {
+        "default_target": "bitstream",
+        "dependencies": {
+            "build_dir": "build/arty_35",
+            "xdc": [
+                "arty.xdc"
+            ]
+        }
+    }
+}

firmware/rtl/raster/script

@@ -0,0 +1,4 @@
+read_verilog raster.v
+synth_xilinx -flatten -nosrl -noclkbuf -nodsp -iopad -nowidelut
+# synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -nowidelut
+write_verilog synth_test_yosys.v

firmware/rtl/raster/synth_test_top.v

@@ -0,0 +1,28 @@
+module top (
+    input clk,
+    input [1:0] btn,
+    input ck_io0,
+    input ck_io1,
+    input ck_io2,
+    input ck_io3,
+    output ck_io4,
+    output ck_io5,
+    output ck_io6,
+    output ck_io7,
+);
+
+  wire bufg;
+  BUFG bufgctrl (
+      .I(clk),
+      .O(bufg)
+  );
+
+  ram_fifo #(.DAT_WID(4), .FIFO_DEPTH(65535/2), .FIFO_DEPTH_WID(16) ) rf (
+	  .clk(bufg),
+	  .rst(0),
+	  .read_enable(btn[0]),
+	  .write_enable(btn[1]),
+	  .write_dat({ck_io0,ck_io1,ck_io2,ck_io3}),
+	  .read_dat({ck_io4,ck_io5,ck_io6,ck_io7})
+  );
+endmodule