diff --git a/build/Dockerfile.litex_f4pga b/build/Dockerfile.litex_f4pga
deleted file mode 100644
index b960804..0000000
--- a/build/Dockerfile.litex_f4pga
+++ /dev/null
@@ -1,42 +0,0 @@
-# Copyright 2023 (C) Peter McGoron
-#
-# This file is a part of Upsilon, a free and open source software project.
-# For license terms, refer to the files in `doc/copying` in the Upsilon 
-# source distribution.
-
-FROM debian:bookworm
-
-ENV FPGA_FAM=xc7
-ENV F4PGA_INSTALL_DIR=/home/user/conda
-
-RUN apt-get update \
-    && apt-get -y upgrade \
-    && apt-get install -y git wget python3 xz-utils bash verilator \
-       m4 device-tree-compiler make gcc-riscv64-unknown-elf \
-    && adduser --quiet --disabled-password user
-
-USER user:user
-WORKDIR /home/user
-
-# F4PGA
-COPY --chown=user:user scripts/install_f4pga_defs.sh /home/user
-RUN chmod +x install_f4pga_defs.sh \
-    && ./install_f4pga_defs.sh \
-    && echo 'source ~/conda/xc7/conda/etc/profile.d/conda.sh' >> /home/user/.bashrc \
-    && echo 'conda activate xc7' >> /home/user/.bashrc \
-    && rm install_f4pga_defs.sh
-
-COPY --chown=user:user f4pga.tar.gz /home/user
-RUN tar -xvf f4pga.tar.gz \
-    && rm f4pga.tar.gz \
-    && cd f4pga/f4pga \ 
-    && bash -c 'source ~/conda/xc7/conda/etc/profile.d/conda.sh; conda activate xc7; pip install . ninja meson'
-
-#LITEX
-COPY --chown=user:user litex/litex_setup.py /home/user
-RUN mkdir /home/user/litex \
-    && chmod +x litex_setup.py \
-    && cd litex/ \
-    && bash -c 'source ~/conda/xc7/conda/etc/profile.d/conda.sh; conda activate xc7; ../litex_setup.py --init --install --user --tag=2023.04' \
-    && rm ../litex_setup.py
-
diff --git a/gateware/rtl/base/base.v.m4 b/gateware/rtl/base/base.v.m4
index dcfdc80..2754d26 100644
--- a/gateware/rtl/base/base.v.m4
+++ b/gateware/rtl/base/base.v.m4
@@ -236,8 +236,8 @@ m4_define(ADC_PORTS_CONTROL_LOOP, (ADC_PORTS + 1))
 	parameter ADC_TYPE2_WID = 16,
 	parameter ADC_TYPE3_WID = 24,
 	parameter ADC_WID_SIZ = 5,
-	parameter ADC_CYCLE_HALF_WAIT = 5,
-	parameter ADC_CYCLE_HALF_WAIT_SIZ = 3,
+	parameter ADC_CYCLE_HALF_WAIT = 60,
+	parameter ADC_CYCLE_HALF_WAIT_SIZ = 7,
 	parameter ADC_POLARITY = 1,
 	parameter ADC_PHASE = 0,
 	/* The ADC takes maximum 527 ns to capture a value.
@@ -312,14 +312,15 @@ m4_dac_switch(DAC_PORTS, 7);
 
 initial test_clock <= 0;
 
+`define MAKE_TEST_CLOCK
 `ifdef MAKE_TEST_CLOCK
-reg [3-1:0] counter = 0;
+reg [8-1:0] counter = 0;
 always @ (posedge clk) begin
 	if (!rst_L) begin
 		counter <= 0;
 		test_clock <= 0;
 	end else begin
-		if (counter == 3) begin
+		if (counter == ADC_CYCLE_HALF_WAIT) begin
 			counter <= 0;
 			test_clock <= !test_clock;
 		end else begin