From 9f76e030286a3adaeaf961a1c98046025666d781 Mon Sep 17 00:00:00 2001
From: Peter McGoron <code@mcgoron.com>
Date: Sat, 3 Feb 2024 00:33:52 +0000
Subject: [PATCH] Minor SPI fixes and Interconnect fix

The previous code did not properly assign all values on all cases,
and did not properly assign values (master interfaces, which are
poorly named because they are the interfaces to the master, connect
to the slave lines directly in the interconnect)
---
 gateware/Makefile                   |  4 ++--
 gateware/rtl/spi/spi_master_ss_wb.v |  4 ++--
 gateware/soc.py                     | 27 ++++++++++++---------------
 3 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/gateware/Makefile b/gateware/Makefile
index 64a917a..7571be5 100644
--- a/gateware/Makefile
+++ b/gateware/Makefile
@@ -28,5 +28,5 @@ arty.dts: csr.json
 arty.dtb: arty.dts
 	dtc -O dtb -o arty.dtb arty.dts
 
-mmio.py: csr2mp.py csr.json
-	python3 csr2mp.py csr.json > mmio.py
+#mmio.py: csr2mp.py csr.json
+#	python3 csr2mp.py csr.json > mmio.py
diff --git a/gateware/rtl/spi/spi_master_ss_wb.v b/gateware/rtl/spi/spi_master_ss_wb.v
index ebf6915..b5d4ed5 100644
--- a/gateware/rtl/spi/spi_master_ss_wb.v
+++ b/gateware/rtl/spi/spi_master_ss_wb.v
@@ -27,7 +27,7 @@ module spi_master_ss_wb
 	input miso,
 	output mosi,
 	output sck_wire,
-	output ss_L
+	output ss_L,
 
 	input wb_cyc,
 	input wb_stb,
@@ -97,7 +97,7 @@ always @ (posedge clk) if (wb_cyc && wb_stb && !wb_ack) begin
 	4'h4: arm <= wb_dat_w[0];
 	4'hC: to_slave <= wb_dat_w;
 	default: ;
-	end
+	endcase
 	wb_ack <= 1;
 end else begin
 	wb_ack <= 0;
diff --git a/gateware/soc.py b/gateware/soc.py
index 4894a76..c58899c 100644
--- a/gateware/soc.py
+++ b/gateware/soc.py
@@ -158,25 +158,21 @@ class PreemptiveInterface(Module, AutoCSR):
         """
 
         def assign_for_case(i):
-            asn = [
-                self.slave.bus.cyc.eq(self.buses[i].cyc),
-                self.slave.bus.stb.eq(self.buses[i].stb),
-                self.slave.bus.we.eq(self.buses[i].we),
-                self.slave.bus.sel.eq(self.buses[i].sel),
-                self.slave.bus.adr.eq(self.buses[i].adr),
-                self.slave.bus.dat_w.eq(self.buses[i].dat_w),
-                self.slave.bus.ack.eq(self.buses[i].ack),
-                self.slave.bus.dat_r.eq(self.buses[i].dat_r),
-            ]
+            asn = [ ]
 
             for j in range(masters_len):
-                if j == i:
-                    continue
                 asn += [
-                    self.buses[i].ack.eq(0),
-                    self.buses[i].ack.eq(0),
+                    self.buses[i].cyc.eq(self.slave.bus.cyc if i == j else 0),
+                    self.buses[i].stb.eq(self.slave.bus.stb if i == j else 0),
+                    self.buses[i].we.eq(self.slave.bus.we if i == j else 0),
+                    self.buses[i].sel.eq(self.slave.bus.sel if i == j else 0),
+                    self.buses[i].adr.eq(self.slave.bus.adr if i == j else 0),
+                    self.buses[i].dat_w.eq(self.slave.bus.dat_w if i == j else 0),
+                    self.buses[i].ack.eq(self.slave.bus.ack if i == j else 0),
+                    self.buses[i].dat_r.eq(self.slave.bus.dat_r if i == j else 0),
+                    self.buses[i].cti.eq(0),
+                    self.buses[i].bte.eq(0),
                 ]
-
             return asn
 
         cases = {"default": assign_for_case(0)}
@@ -401,6 +397,7 @@ class UpsilonSoC(SoCCore):
     def add_picorv32(self):
         self.submodules.picorv32 = pr = PicoRV32()
         self.bus.add_slave("picorv32_master_bram", pr.bram_iface.buses[0], pr.bram.region)
+        pr.finalize()
 
     def __init__(self,
                  variant="a7-100",