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boot currently loops at LiteX logo: this fixes it

This commit is contained in:
Peter McGoron 2024-02-04 18:59:35 +00:00
parent 7af775e46d
commit a10ad772bc
1 changed files with 7 additions and 7 deletions
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14
gateware/soc.py
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@ -447,16 +447,16 @@ class UpsilonSoC(SoCCore):
Since Yosys doesn't support modern Verilog, only put preprocessed Since Yosys doesn't support modern Verilog, only put preprocessed
(if applicable) files here. (if applicable) files here.
""" """
platform.add_source("rtl/picorv32/picorv32.v") #platform.add_source("rtl/picorv32/picorv32.v")
platform.add_source("rtl/spi/spi_master.v") #platform.add_source("rtl/spi/spi_master.v")
platform.add_source("rtl/spi/spi_master_ss.v") #platform.add_source("rtl/spi/spi_master_ss.v")
platform.add_source("rtl/spi/spi_master_ss_wb.v") #platform.add_source("rtl/spi/spi_master_ss_wb.v")
platform.add_source("rtl/bram/bram.v") #platform.add_source("rtl/bram/bram.v")
# SoCCore does not have sane defaults (no integrated rom) # SoCCore does not have sane defaults (no integrated rom)
SoCCore.__init__(self, SoCCore.__init__(self,
clk_freq=sys_clk_freq, clk_freq=sys_clk_freq,
toolchain="symbiflow", toolchain="f4pga",
platform = platform, platform = platform,
bus_standard = "wishbone", bus_standard = "wishbone",
ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr - Upsilon", ident = f"Arty-{variant} F4PGA LiteX VexRiscV Zephyr - Upsilon",
@ -500,7 +500,7 @@ class UpsilonSoC(SoCCore):
# Add pins # Add pins
platform.add_extension(io) platform.add_extension(io)
self.add_picorv32() #self.add_picorv32()
def main(): def main():
""" Add modifications to SoC variables here """ """ Add modifications to SoC variables here """