ram_shim: add and lint
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@ -28,20 +28,20 @@ localparam WAIT_ON_COMMIT_DEASSERT = 3;
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reg [2:0] state = WAIT_ON_COMMIT;
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reg [2:0] state = WAIT_ON_COMMIT;
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reg [MAX_BYTE_WID-1:0] offset = 0;
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reg [MAX_BYTE_WID-1:0] offset = 0;
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assign addr = BASE_ADDR + offset;
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assign addr = BASE_ADDR + {{(RAM_WID - MAX_BYTE_WID){1'b0}}, offset};
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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case (state)
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case (state)
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WAIT_ON_COMMIT: if (commit) begin
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WAIT_ON_COMMIT: if (commit) begin
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word <= data[RAM_WORD-1:0];
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word <= data[RAM_WORD-1:0];
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write <= 1;
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write <= 1;
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state <= HIGH_WORD;
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state <= HIGH_WORD_LOAD;
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end
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end
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HIGH_WORD_LOAD: if (valid) begin
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HIGH_WORD_LOAD: if (valid) begin
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offset <= offset + (RAM_WORD/2);
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offset <= offset + (RAM_WORD/2);
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write <= 0;
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write <= 0;
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word <= {(RAM_WORD*2 - DAT_WID){word[DAT_WID-1]},
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word <= {{(RAM_WORD*2 - DAT_WID){data[DAT_WID-1]}},
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word[DAT_WID-1:RAM_WORD]};
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data[DAT_WID-1:RAM_WORD]};
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state <= WAIT_ON_HIGH_WORD;
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state <= WAIT_ON_HIGH_WORD;
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end
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end
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WAIT_ON_HIGH_WORD: if (!write) begin
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WAIT_ON_HIGH_WORD: if (!write) begin
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