firmware is a form of software; gateware is the equivalent for FGPAs

2023-06-14 15:31:49 -04:00 · 2023-06-14 15:31:49 -04:00 · a560e51991
parent 59a7ca9de5
commit a560e51991
73 changed files with 7 additions and 7 deletions
--- a/build/Makefile
+++ b/build/Makefile
@ -27,16 +27,16 @@ hardware-copy: upsilon-hardware.tar.gz
 hardware-execute:
 	docker exec -ti upsilon-hardware /bin/bash -lc ' \
 		tar -xvf upsilon-hardware.tar.gz && \
-		cd upsilon/firmware && \
+		cd upsilon/gateware && \
 		source ~/conda/xc7/conda/etc/profile.d/conda.sh && \
 		conda activate xc7 && \
 		make clean && make'
 hardware-shell:
 	docker exec -ti upsilon-hardware /bin/bash -l
 hardware-get:
-	docker cp upsilon-hardware:/home/user/upsilon/firmware/build/digilent_arty/gateware/digilent_arty.bit ../boot/
+	docker cp upsilon-hardware:/home/user/upsilon/gateware/build/digilent_arty/gateware/digilent_arty.bit ../boot/
-	docker cp upsilon-hardware:/home/user/upsilon/firmware/arty.dtb ../boot/
+	docker cp upsilon-hardware:/home/user/upsilon/gateware/arty.dtb ../boot/
-	docker cp upsilon-hardware:/home/user/upsilon/firmware/csr.json ../boot/
+	docker cp upsilon-hardware:/home/user/upsilon/gateware/csr.json ../boot/
 hardware-clean:
 	-docker container stop upsilon-hardware
 	-docker container rm upsilon-hardware
@ -77,7 +77,7 @@ verilator-shell:
 verilator-execute:
 	docker exec -ti upsilon-verilator /bin/bash -c ' \
 		tar -xvf upsilon-hardware.tar.gz && \
-		cd upsilon/firmware && \
+		cd upsilon/gateware && \
 		make clean && \
 		make test \
 		'
@ -142,7 +142,7 @@ litex:
 		git checkout -B upsilon_stable c6ccb626e88168045edacced3743f6bd98746742
 upsilon-hardware.tar.gz:
-	tar -czvf upsilon-hardware.tar.gz ../firmware/
+	tar -czvf upsilon-hardware.tar.gz ../gateware/
 upsilon-buildroot.tar.gz:
 	tar -czvf upsilon-buildroot.tar.gz ../buildroot/
 # This script only works for GNU tar. It renames the extraction directory.
--- a/doc/copying/README.md
+++ b/doc/copying/README.md
@ -1,7 +1,7 @@
 Upsilon is a copyleft hardware project, which brings its own difficulties.
 Upsilon is dual-licensed in many locations.
-The files under `firmware/` are disjunctive dual-licensed under the CERN-OHL-S
+The files under `gateware/` are disjunctive dual-licensed under the CERN-OHL-S
 v2.0 (or any later version), or the GNU GPL v3.0 (or any later version).
 The files under `buildroot/` and `opensbi/` are licensed under a BSD
--- a/gateware/A7-constraints.xdc
+++ b/gateware/A7-constraints.xdc
--- a/gateware/Makefile
+++ b/gateware/Makefile
--- a/gateware/generate_csr_locations.py
+++ b/gateware/generate_csr_locations.py
--- a/gateware/rtl/Makefile
+++ b/gateware/rtl/Makefile
--- a/gateware/rtl/base/Makefile
+++ b/gateware/rtl/base/Makefile
--- a/gateware/rtl/base/base.v.m4
+++ b/gateware/rtl/base/base.v.m4
--- a/gateware/rtl/common.makefile
+++ b/gateware/rtl/common.makefile
--- a/gateware/rtl/control_loop/Makefile
+++ b/gateware/rtl/control_loop/Makefile
--- a/gateware/rtl/control_loop/adc_sim.v
+++ b/gateware/rtl/control_loop/adc_sim.v
--- a/gateware/rtl/control_loop/boothmul.v
+++ b/gateware/rtl/control_loop/boothmul.v
--- a/gateware/rtl/control_loop/boothmul_sim.cpp
+++ b/gateware/rtl/control_loop/boothmul_sim.cpp
--- a/gateware/rtl/control_loop/control_loop.v.m4
+++ b/gateware/rtl/control_loop/control_loop.v.m4
--- a/gateware/rtl/control_loop/control_loop_cmds.h.m4
+++ b/gateware/rtl/control_loop/control_loop_cmds.h.m4
--- a/gateware/rtl/control_loop/control_loop_cmds.m4
+++ b/gateware/rtl/control_loop/control_loop_cmds.m4
--- a/gateware/rtl/control_loop/control_loop_cmds.vh.m4
+++ b/gateware/rtl/control_loop/control_loop_cmds.vh.m4
--- a/gateware/rtl/control_loop/control_loop_math.v.m4
+++ b/gateware/rtl/control_loop/control_loop_math.v.m4
--- a/gateware/rtl/control_loop/control_loop_math_implementation.cpp
+++ b/gateware/rtl/control_loop/control_loop_math_implementation.cpp
--- a/gateware/rtl/control_loop/control_loop_math_implementation.h
+++ b/gateware/rtl/control_loop/control_loop_math_implementation.h
--- a/gateware/rtl/control_loop/control_loop_math_sim.cpp
+++ b/gateware/rtl/control_loop/control_loop_math_sim.cpp
--- a/gateware/rtl/control_loop/control_loop_sim.cpp
+++ b/gateware/rtl/control_loop/control_loop_sim.cpp
--- a/gateware/rtl/control_loop/control_loop_sim_interactive.cpp
+++ b/gateware/rtl/control_loop/control_loop_sim_interactive.cpp
--- a/gateware/rtl/control_loop/control_loop_sim_top.v
+++ b/gateware/rtl/control_loop/control_loop_sim_top.v
--- a/gateware/rtl/control_loop/dac_sim.v
+++ b/gateware/rtl/control_loop/dac_sim.v
--- a/gateware/rtl/control_loop/intro.md
+++ b/gateware/rtl/control_loop/intro.md
--- a/gateware/rtl/control_loop/intsat.v
+++ b/gateware/rtl/control_loop/intsat.v
--- a/gateware/rtl/control_loop/intsat_sim.cpp
+++ b/gateware/rtl/control_loop/intsat_sim.cpp
--- a/gateware/rtl/control_loop/intsat_testbench.v
+++ b/gateware/rtl/control_loop/intsat_testbench.v
--- a/gateware/rtl/control_loop/sign_extend.v
+++ b/gateware/rtl/control_loop/sign_extend.v
--- a/gateware/rtl/control_loop/yosys_test.sh
+++ b/gateware/rtl/control_loop/yosys_test.sh
--- a/gateware/rtl/raster/Makefile
+++ b/gateware/rtl/raster/Makefile
--- a/gateware/rtl/raster/arty.xdc
+++ b/gateware/rtl/raster/arty.xdc
--- a/gateware/rtl/raster/flow.json
+++ b/gateware/rtl/raster/flow.json
--- a/gateware/rtl/raster/ram_fifo.v
+++ b/gateware/rtl/raster/ram_fifo.v
--- a/gateware/rtl/raster/ram_fifo_dual_port.v
+++ b/gateware/rtl/raster/ram_fifo_dual_port.v
--- a/gateware/rtl/raster/ram_fifo_sim.cpp
+++ b/gateware/rtl/raster/ram_fifo_sim.cpp
--- a/gateware/rtl/raster/ram_shim.v
+++ b/gateware/rtl/raster/ram_shim.v
--- a/gateware/rtl/raster/ram_shim_cmds.vh
+++ b/gateware/rtl/raster/ram_shim_cmds.vh
--- a/gateware/rtl/raster/ram_shim_sim.cpp
+++ b/gateware/rtl/raster/ram_shim_sim.cpp
--- a/gateware/rtl/raster/raster.v
+++ b/gateware/rtl/raster/raster.v
--- a/gateware/rtl/raster/raster_cmds.vh
+++ b/gateware/rtl/raster/raster_cmds.vh
--- a/gateware/rtl/raster/raster_sim.cpp
+++ b/gateware/rtl/raster/raster_sim.cpp
--- a/gateware/rtl/raster/raster_sim.v
+++ b/gateware/rtl/raster/raster_sim.v
--- a/gateware/rtl/raster/script
+++ b/gateware/rtl/raster/script
--- a/gateware/rtl/raster/synth_test_top.v
+++ b/gateware/rtl/raster/synth_test_top.v
--- a/gateware/rtl/spi/Makefile
+++ b/gateware/rtl/spi/Makefile
--- a/gateware/rtl/spi/ramp.v
+++ b/gateware/rtl/spi/ramp.v
--- a/gateware/rtl/spi/spi_master.v
+++ b/gateware/rtl/spi/spi_master.v
--- a/gateware/rtl/spi/spi_master_no_read.v
+++ b/gateware/rtl/spi/spi_master_no_read.v
--- a/gateware/rtl/spi/spi_master_no_write.v
+++ b/gateware/rtl/spi/spi_master_no_write.v
--- a/gateware/rtl/spi/spi_master_ss.v
+++ b/gateware/rtl/spi/spi_master_ss.v
--- a/gateware/rtl/spi/spi_master_ss_no_read.v
+++ b/gateware/rtl/spi/spi_master_ss_no_read.v
--- a/gateware/rtl/spi/spi_master_ss_no_write.v
+++ b/gateware/rtl/spi/spi_master_ss_no_write.v
--- a/gateware/rtl/spi/spi_master_ss_template.v
+++ b/gateware/rtl/spi/spi_master_ss_template.v
--- a/gateware/rtl/spi/spi_slave.v
+++ b/gateware/rtl/spi/spi_slave.v
--- a/gateware/rtl/spi/spi_slave_no_read.v
+++ b/gateware/rtl/spi/spi_slave_no_read.v
--- a/gateware/rtl/spi/spi_slave_no_write.v
+++ b/gateware/rtl/spi/spi_slave_no_write.v
--- a/gateware/rtl/spi/spi_switch.v
+++ b/gateware/rtl/spi/spi_switch.v
--- a/gateware/rtl/spi/spi_switch_sim.cpp
+++ b/gateware/rtl/spi/spi_switch_sim.cpp
--- a/gateware/rtl/testbench.hpp
+++ b/gateware/rtl/testbench.hpp
--- a/gateware/rtl/util.hpp
+++ b/gateware/rtl/util.hpp
--- a/gateware/rtl/waveform/Makefile
+++ b/gateware/rtl/waveform/Makefile
--- a/gateware/rtl/waveform/bram_dma.cpp
+++ b/gateware/rtl/waveform/bram_dma.cpp
--- a/gateware/rtl/waveform/bram_dma.hpp
+++ b/gateware/rtl/waveform/bram_dma.hpp
--- a/gateware/rtl/waveform/bram_interface.v
+++ b/gateware/rtl/waveform/bram_interface.v
--- a/gateware/rtl/waveform/bram_interface_sim.cpp
+++ b/gateware/rtl/waveform/bram_interface_sim.cpp
--- a/gateware/rtl/waveform/bram_interface_sim.v
+++ b/gateware/rtl/waveform/bram_interface_sim.v
--- a/gateware/rtl/waveform/dma_sim.v
+++ b/gateware/rtl/waveform/dma_sim.v
--- a/gateware/rtl/waveform/waveform.v
+++ b/gateware/rtl/waveform/waveform.v
--- a/gateware/rtl/waveform/waveform_sim.cpp
+++ b/gateware/rtl/waveform/waveform_sim.cpp
--- a/gateware/rtl/waveform/waveform_sim.v
+++ b/gateware/rtl/waveform/waveform_sim.v
--- a/gateware/soc.py
+++ b/gateware/soc.py