diff --git a/firmware/rtl/control_loop/control_loop.v b/firmware/rtl/control_loop/control_loop.v
index 45d3a85..a289842 100644
--- a/firmware/rtl/control_loop/control_loop.v
+++ b/firmware/rtl/control_loop/control_loop.v
@@ -34,7 +34,7 @@ module control_loop
 	parameter DAC_PHASE = 1,
 	parameter DAC_CYCLE_HALF_WAIT = 10,
 	parameter DAC_CYCLE_HALF_WAIT_SIZ = 4,
-	parameter DAC_SS_WAIT = 2,
+	parameter DAC_SS_WAIT = 5,
 	parameter DAC_SS_WAIT_SIZ = 3
 ) (
 	input clk,
@@ -60,8 +60,6 @@ module control_loop
 
 reg dac_arm;
 reg dac_finished;
-reg dac_ss = 0;
-assign dac_ss_L = !dac_ss;
 
 reg [DAC_WID-1:0] to_dac;
 /* verilator lint_off UNUSED */
@@ -351,7 +349,6 @@ always @ (posedge clk) begin
 			timer <= 0;
 		end else if (dac_finished) begin
 			state <= CYCLE_START;
-			dac_ss <= 0;
 			dac_arm <= 0;
 			timer <= 0;
 			stored_dac_val <= from_dac[DAC_DATA_WID-1:0];
diff --git a/firmware/rtl/control_loop/dac_sim.v b/firmware/rtl/control_loop/dac_sim.v
index f012569..09659a5 100644
--- a/firmware/rtl/control_loop/dac_sim.v
+++ b/firmware/rtl/control_loop/dac_sim.v
@@ -25,8 +25,6 @@ reg [WID-4-1:0] ctrl_register = 0;
 always @ (posedge clk) begin
 	if (spi_fin) begin
 		rdy <= 0;
-		/* read current value. TODO: lower bit DACs have zero
-		 * padding between register and DAC value. */
 		case (from_master[WID-1:WID-4])
 		4'b1001: begin
 			to_master <= {4'b1001, curset};
@@ -42,7 +40,7 @@ always @ (posedge clk) begin
 		4'b1010: begin
 			to_master <= {4'b1010, ctrl_register};
 		end
-		default: ;
+		default: to_master <= 0;
 		endcase
 	end else if (!rdy) begin
 		rdy <= 1;