autoapproach: add reset test to bram
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@ -6,7 +6,8 @@
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module autoapproach #(
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module autoapproach #(
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parameter DAC_WID = 24,
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parameter DAC_WID = 24,
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parameter DAC_DATA_WID = 20,
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parameter DAC_DATA_WID = 20,
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parameter ADC_WID = 24
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parameter ADC_WID = 24,
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parameter TIMER_WID = 32
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) (
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) (
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input clk,
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input clk,
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input arm,
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input arm,
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@ -15,6 +16,7 @@ module autoapproach #(
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input polarity,
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input polarity,
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input [ADC_WID-1:0] setpoint,
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input [ADC_WID-1:0] setpoint,
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input [TIMER_WID-1:0] time_to_wait,
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/* BRAM memory interface. Each pulse returns the next value in
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/* BRAM memory interface. Each pulse returns the next value in
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* the sequence, and also informs the module if the sequence
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* the sequence, and also informs the module if the sequence
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@ -39,21 +41,32 @@ module autoapproach #(
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localparam WAIT_ON_ARM = 0;
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localparam WAIT_ON_ARM = 0;
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localparam RECV_WORD = 1;
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localparam DO_WAIT = 1;
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localparam WAIT_ON_DAC = 2;
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localparam RECV_WORD = 2;
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localparam WAIT_ON_DETECTION = 3;
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localparam WAIT_ON_DAC = 3;
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localparam DETECTED = 4;
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localparam WAIT_ON_DETECTION = 4;
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localparam DETECTED = 5;
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reg [2:0] state = WAIT_ON_ARM;
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reg [2:0] state = WAIT_ON_ARM;
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reg [TIMER_WID-1:0] wait_timer = 0;
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always @ (posedge clk) case (state)
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always @ (posedge clk) case (state)
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WAIT_ON_ARM: if (arm) begin
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WAIT_ON_ARM: if (arm) begin
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state <= RECV_WORD;
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state <= DO_WAIT;
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word_next <= 1;
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stopped <= 0;
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stopped <= 0;
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wait_timer <= time_to_wait;
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end else begin
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end else begin
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stopped <= 1;
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stopped <= 1;
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word_rst <= 1;
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word_rst <= 1;
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end
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end
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DO_WAIT: if (!arm) begin
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state <= WAIT_ON_ARM;
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end else if (wait_timer == 0) begin
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word_next <= 1;
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state <= RECV_WORD;
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end else begin
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wait_timer <= wait_timer - 1;
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end
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RECV_WORD: if (word_ok) begin
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RECV_WORD: if (word_ok) begin
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dac_out <= {4'b0001, word};
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dac_out <= {4'b0001, word};
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dac_arm <= 1;
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dac_arm <= 1;
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@ -86,6 +86,9 @@ reg [WORD_AMNT_WID-1:0] auto_cntr = 0;
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always @ (posedge clk) if (word_rst) begin
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always @ (posedge clk) if (word_rst) begin
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auto_cntr <= 0;
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auto_cntr <= 0;
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word_ok <= 0;
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word_last <= 0;
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word <= 0;
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end else if (word_next && !word_ok) begin
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end else if (word_next && !word_ok) begin
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if (refresh_state == WAIT_ON_REFRESH) begin
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if (refresh_state == WAIT_ON_REFRESH) begin
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word <= backing_buffer[auto_cntr];
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word <= backing_buffer[auto_cntr];
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@ -86,6 +86,24 @@ static void test_aa_read_1() {
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my_assert(ind == WORD_AMNT, "second read value %zu != %d\n", ind, WORD_AMNT);
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my_assert(ind == WORD_AMNT, "second read value %zu != %d\n", ind, WORD_AMNT);
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}
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}
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static void test_aa_read_interrupted() {
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size_t ind = 0;
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mod->word_next = 1;
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run_clock();
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for (int i = 0; i < 100; i++) {
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handle_read_aa(ind);
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run_clock();
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my_assert(!mod->word_last, "too many reads");
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}
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mod->word_rst = 1;
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run_clock();
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mod->word_rst = 0;
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run_clock();
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test_aa_read_1();
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}
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static void refresh_data() {
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static void refresh_data() {
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for (size_t i = 0; i < RAM_WID; i++) {
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for (size_t i = 0; i < RAM_WID; i++) {
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ram_refresh_data[i] = mask_extend(rand(), 20);
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ram_refresh_data[i] = mask_extend(rand(), 20);
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@ -108,10 +126,15 @@ static void refresh_data() {
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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init(argc, argv);
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init(argc, argv);
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printf("test basic read/write\n");
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refresh_data();
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refresh_data();
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test_aa_read_1();
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test_aa_read_1();
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refresh_data();
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refresh_data();
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test_aa_read_1();
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test_aa_read_1();
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printf("test resetting\n");
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test_aa_read_interrupted();
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printf("ok\n");
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printf("ok\n");
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return 0;
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return 0;
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