autoapproach: add reset test to bram

This commit is contained in:
Peter McGoron 2023-01-23 04:58:38 +00:00
parent 65b1436e0b
commit b1ba3434cf
3 changed files with 46 additions and 7 deletions

View File

@ -6,7 +6,8 @@
module autoapproach #( module autoapproach #(
parameter DAC_WID = 24, parameter DAC_WID = 24,
parameter DAC_DATA_WID = 20, parameter DAC_DATA_WID = 20,
parameter ADC_WID = 24 parameter ADC_WID = 24,
parameter TIMER_WID = 32
) ( ) (
input clk, input clk,
input arm, input arm,
@ -15,6 +16,7 @@ module autoapproach #(
input polarity, input polarity,
input [ADC_WID-1:0] setpoint, input [ADC_WID-1:0] setpoint,
input [TIMER_WID-1:0] time_to_wait,
/* BRAM memory interface. Each pulse returns the next value in /* BRAM memory interface. Each pulse returns the next value in
* the sequence, and also informs the module if the sequence * the sequence, and also informs the module if the sequence
@ -39,21 +41,32 @@ module autoapproach #(
localparam WAIT_ON_ARM = 0; localparam WAIT_ON_ARM = 0;
localparam RECV_WORD = 1; localparam DO_WAIT = 1;
localparam WAIT_ON_DAC = 2; localparam RECV_WORD = 2;
localparam WAIT_ON_DETECTION = 3; localparam WAIT_ON_DAC = 3;
localparam DETECTED = 4; localparam WAIT_ON_DETECTION = 4;
localparam DETECTED = 5;
reg [2:0] state = WAIT_ON_ARM; reg [2:0] state = WAIT_ON_ARM;
reg [TIMER_WID-1:0] wait_timer = 0;
always @ (posedge clk) case (state) always @ (posedge clk) case (state)
WAIT_ON_ARM: if (arm) begin WAIT_ON_ARM: if (arm) begin
state <= RECV_WORD; state <= DO_WAIT;
word_next <= 1;
stopped <= 0; stopped <= 0;
wait_timer <= time_to_wait;
end else begin end else begin
stopped <= 1; stopped <= 1;
word_rst <= 1; word_rst <= 1;
end end
DO_WAIT: if (!arm) begin
state <= WAIT_ON_ARM;
end else if (wait_timer == 0) begin
word_next <= 1;
state <= RECV_WORD;
end else begin
wait_timer <= wait_timer - 1;
end
RECV_WORD: if (word_ok) begin RECV_WORD: if (word_ok) begin
dac_out <= {4'b0001, word}; dac_out <= {4'b0001, word};
dac_arm <= 1; dac_arm <= 1;

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@ -86,6 +86,9 @@ reg [WORD_AMNT_WID-1:0] auto_cntr = 0;
always @ (posedge clk) if (word_rst) begin always @ (posedge clk) if (word_rst) begin
auto_cntr <= 0; auto_cntr <= 0;
word_ok <= 0;
word_last <= 0;
word <= 0;
end else if (word_next && !word_ok) begin end else if (word_next && !word_ok) begin
if (refresh_state == WAIT_ON_REFRESH) begin if (refresh_state == WAIT_ON_REFRESH) begin
word <= backing_buffer[auto_cntr]; word <= backing_buffer[auto_cntr];

View File

@ -86,6 +86,24 @@ static void test_aa_read_1() {
my_assert(ind == WORD_AMNT, "second read value %zu != %d\n", ind, WORD_AMNT); my_assert(ind == WORD_AMNT, "second read value %zu != %d\n", ind, WORD_AMNT);
} }
static void test_aa_read_interrupted() {
size_t ind = 0;
mod->word_next = 1;
run_clock();
for (int i = 0; i < 100; i++) {
handle_read_aa(ind);
run_clock();
my_assert(!mod->word_last, "too many reads");
}
mod->word_rst = 1;
run_clock();
mod->word_rst = 0;
run_clock();
test_aa_read_1();
}
static void refresh_data() { static void refresh_data() {
for (size_t i = 0; i < RAM_WID; i++) { for (size_t i = 0; i < RAM_WID; i++) {
ram_refresh_data[i] = mask_extend(rand(), 20); ram_refresh_data[i] = mask_extend(rand(), 20);
@ -108,10 +126,15 @@ static void refresh_data() {
int main(int argc, char **argv) { int main(int argc, char **argv) {
init(argc, argv); init(argc, argv);
printf("test basic read/write\n");
refresh_data(); refresh_data();
test_aa_read_1(); test_aa_read_1();
refresh_data(); refresh_data();
test_aa_read_1(); test_aa_read_1();
printf("test resetting\n");
test_aa_read_interrupted();
printf("ok\n"); printf("ok\n");
return 0; return 0;