From be03d68e6fdd0af85e77f36597fa7122f28cc7b5 Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Tue, 30 May 2023 16:01:32 -0400 Subject: [PATCH] more work on linux upsilon --- .gitignore | 1 - firmware/Makefile | 12 +++-- firmware/soc.py | 6 ++- opensbi/litex/vexriscv/config.mk | 30 ----------- opensbi/litex/vexriscv/litex.c | 67 ------------------------ opensbi/litex/vexriscv/platform.c | 85 ++++++++----------------------- 6 files changed, 31 insertions(+), 170 deletions(-) delete mode 100644 opensbi/litex/vexriscv/config.mk delete mode 100644 opensbi/litex/vexriscv/litex.c diff --git a/.gitignore b/.gitignore index 58713d3..58c0a2c 100644 --- a/.gitignore +++ b/.gitignore @@ -16,7 +16,6 @@ firmware/rtl/control_loop/control_loop_cmds.h firmware/rtl/raster/ram_shim_cmds.h firmware/rtl/raster/raster_cmds.h firmware/rtl/base/base.v -firmware/rtl/control_loop/boothmul.v firmware/rtl/control_loop/control_loop.v firmware/rtl/control_loop/control_loop_cmds.vh firmware/rtl/control_loop/control_loop_math.v diff --git a/firmware/Makefile b/firmware/Makefile index 6aeedf3..72f4bf8 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -6,14 +6,16 @@ all: rtl_codegen build/digilent_arty/digilent_arty.bit overlay.dts overlay.cmake rtl_codegen: cd rtl && make -build/digilent_arty/digilent_arty.bit: soc.py +csr.json build/digilent_arty/digilent_arty.bit: soc.py python3 soc.py clean: - rm -rf build csr.json overlay.config overlay.dts pin_io.h + rm -rf build csr.json overlay.config overlay.dts pin_io.h arty.dts arty.dtb cd rtl && make clean -overlay.dts overlay.cmake: csr.json litex_json2dts_zephyr.py - # NOTE: Broken in LiteX 2022.4. - $(DEVICETREE_GEN_DIR)/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.cmake csr.json + +arty.dts: csr.json + litex_json2dts_linux.py csr.json > arty.dts +arty.dtb: arty.dts + dtc -O dtb -o arty.dtb arty.dts pin_io.c: csr.json generate_csr_locations.py python3 generate_csr_locations.py > pin_io.c diff --git a/firmware/soc.py b/firmware/soc.py index 0277541..78d2e61 100644 --- a/firmware/soc.py +++ b/firmware/soc.py @@ -1,3 +1,4 @@ +########################################################################## # Portions of this file incorporate code licensed under the # BSD 2-Clause License. # @@ -30,6 +31,7 @@ # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +########################################################################## # There is nothing fundamental about the Arty A7(35|100)T to this # design, but another eval board will require some porting. @@ -221,7 +223,7 @@ class _CRG(Module): if with_dram: self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) -class CryoSNOM1SoC(SoCCore): +class UpsilonSoC(SoCCore): def __init__(self, variant): sys_clk_freq = int(100e6) platform = board_spec.Platform(variant=variant, toolchain="f4pga") @@ -291,7 +293,7 @@ class CryoSNOM1SoC(SoCCore): self.submodules.base = Base(ClockSignal(), self.sdram, platform) def main(): - soc = CryoSNOM1SoC("a7-100") + soc =UpsilonSoC("a7-100") builder = Builder(soc, csr_json="csr.json", compile_software=True) builder.build() diff --git a/opensbi/litex/vexriscv/config.mk b/opensbi/litex/vexriscv/config.mk deleted file mode 100644 index 5b89a1d..0000000 --- a/opensbi/litex/vexriscv/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# SPDX-License-Identifier: BSD-2-Clause -# -# Copyright (c) 2020 Florent Kermarrec -# Copyright (c) 2020 Dolu1990 -# - -# Compiler flags -platform-cppflags-y = -platform-cflags-y = -platform-asflags-y = -platform-ldflags-y = - -# Command for platform specific "make run" -platform-runcmd = echo LiteX/VexRiscv SMP - -PLATFORM_RISCV_XLEN = 32 -PLATFORM_RISCV_ABI = ilp32 -PLATFORM_RISCV_ISA = rv32ima -PLATFORM_RISCV_CODE_MODEL = medany - -# Blobs to build -FW_TEXT_START=0x40F00000 -FW_DYNAMIC=y -FW_JUMP=y -FW_JUMP_ADDR=0x40000000 -FW_JUMP_FDT_ADDR=0x40EF0000 -FW_PAYLOAD=y -FW_PAYLOAD_OFFSET=0x40000000 -FW_PAYLOAD_FDT_ADDR=0x40EF0000 diff --git a/opensbi/litex/vexriscv/litex.c b/opensbi/litex/vexriscv/litex.c deleted file mode 100644 index 6210df7..0000000 --- a/opensbi/litex/vexriscv/litex.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2020 Florent Kermarrec - * Copyright (c) 2020 Dolu1990 - * - */ - -#include - -#define UART_EV_TX 0x1 -#define UART_EV_RX 0x2 - -#define MMPTR(a) (*((volatile uint32_t *)(a))) - -static inline void csr_write_simple(unsigned long v, unsigned long a) -{ - MMPTR(a) = v; -} - -static inline unsigned long csr_read_simple(unsigned long a) -{ - return MMPTR(a); -} - -#define CSR_BASE 0xf0000000L - -static inline uint8_t uart_rxtx_read(void) { - return csr_read_simple(CSR_BASE + 0x1000L); -} -static inline void uart_rxtx_write(uint8_t v) { - csr_write_simple(v, CSR_BASE + 0x1000L); -} - -static inline uint8_t uart_txfull_read(void) { - return csr_read_simple(CSR_BASE + 0x1004L); -} - -static inline uint8_t uart_rxempty_read(void) { - return csr_read_simple(CSR_BASE + 0x1008L); -} - -static inline void uart_ev_pending_write(uint8_t v) { - csr_write_simple(v, CSR_BASE + 0x1010L); -} - -static inline uint8_t uart_txempty_read(void) { - return csr_read_simple(CSR_BASE + 0x1018L); -} -static inline uint8_t uart_rxfull_read(void) { - return csr_read_simple(CSR_BASE + 0x101cL); -} - - -void vex_putc(char c){ - while (uart_txfull_read()); - uart_rxtx_write(c); - uart_ev_pending_write(UART_EV_TX); -} - -int vex_getc(void){ - char c; - if (uart_rxempty_read()) return -1; - c = uart_rxtx_read(); - uart_ev_pending_write(UART_EV_RX); - return c; -} diff --git a/opensbi/litex/vexriscv/platform.c b/opensbi/litex/vexriscv/platform.c index 2c3a297..9d64f65 100644 --- a/opensbi/litex/vexriscv/platform.c +++ b/opensbi/litex/vexriscv/platform.c @@ -11,55 +11,30 @@ #include #include #include -#include -#include +#include #include - /* clang-format off */ -#define VEX_HART_COUNT 8 +#define VEX_HART_COUNT 1 #define VEX_PLATFORM_FEATURES (SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_MFAULTS_DELEGATION) #define VEX_CLINT_ADDR 0xF0010000 -#define VEX_HART_STACK_SIZE 8192 +#define VEX_HART_STACK_SIZE SBI_PLATFORM_DEFAULT_STACK_SIZE /* clang-format on */ static struct clint_data clint = {VEX_CLINT_ADDR, 0, VEX_HART_COUNT, true}; +static int vex_early_init(bool cold_boot) +{ + return 0; +} + static int vex_final_init(bool cold_boot) { return 0; } -static u32 vex_pmp_region_count(u32 hartid) -{ - return 0; -} - -static int vex_pmp_region_info(u32 hartid, u32 index, ulong *prot, ulong *addr, - ulong *log2size) -{ - int ret = 0; - - switch (index) { - default: - ret = -1; - break; - }; - - return ret; -} - - -extern void vex_putc(char ch); -extern int vex_getc(void); - -static int vex_console_init(void) -{ - return 0; -} - static int vex_irqchip_init(bool cold_boot) { return 0; @@ -90,41 +65,21 @@ static int vex_timer_init(bool cold_boot) return clint_warm_timer_init(); } -static int vex_system_reset(u32 type) -{ - /* Tell the "finisher" that the simulation - * was successful so that QEMU exits - */ - - return 0; -} - const struct sbi_platform_operations platform_ops = { - .pmp_region_count = vex_pmp_region_count, - .pmp_region_info = vex_pmp_region_info, - .final_init = vex_final_init, - .console_putc = vex_putc, - .console_getc = vex_getc, - .console_init = vex_console_init, - .irqchip_init = vex_irqchip_init, - .ipi_send = clint_ipi_send, - .ipi_clear = clint_ipi_clear, - .ipi_init = vex_ipi_init, - .timer_value = clint_timer_value, - .timer_event_stop = clint_timer_event_stop, - .timer_event_start = clint_timer_event_start, - .timer_init = vex_timer_init, - .system_reset = vex_system_reset + .early_init = vex_early_init, + .final_init = vex_final_init, + .irqchip_init = vex_irqchip_init, + .ipi_init = vex_ipi_init, + .timer_init = vex_timer_init }; const struct sbi_platform platform = { - .opensbi_version = OPENSBI_VERSION, - .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), - .name = "LiteX / VexRiscv-SMP", - .features = VEX_PLATFORM_FEATURES, - .hart_count = VEX_HART_COUNT, - .hart_stack_size = VEX_HART_STACK_SIZE, - .platform_ops_addr = (unsigned long)&platform_ops + .opensbi_version = OPENSBI_VERSION, + .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), + .name = "LiteX / VexRiscv", + .features = VEX_PLATFORM_FEATURES, + .hart_count = VEX_HART_COUNT, + .hart_stack_size = VEX_HART_STACK_SIZE, + .platform_ops_addr = (unsigned long)&platform_ops }; -