bram: more refactor

firmware/rtl/autoapproach/bram_interface_sim.cpp

@@ -1,10 +1,5 @@
-#include <memory>
-#include <cassert>
 #include <limits>
-#include <cstdint>
-#include <cstring>
 #include <cstdlib>
-#include <iostream>
 #include <random>
 #include <unistd.h>
 #include <verilated.h>
@@ -118,9 +113,8 @@ static void refresh_data() {
 }
 
 int main(int argc, char *argv[]) {
-	Verilated::commandArgs(argc, argv);
 	Verilated::traceEverOn(true);
-	tb = new TB<Vbram_interface>();
+	tb = new TB<Vbram_interface>(argc, argv);
 
 	printf("test basic read/write\n");
 	refresh_data();

firmware/rtl/testbench.hpp

@@ -1,13 +1,19 @@
 #pragma once
 #include <cstdint>
+#include <verilated.h>
 
 /* https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html */
 template <class TOP> class TB {
 	int tick_count;
 	int bailout;
 
-	public: TOP mod;
-	TB(int _bailout = 0) : mod(), bailout(_bailout) {
+	public:
+	TOP mod;
+	VerilatedContext vc;
+
+	TB(int argc, char *argv[], int _bailout = 0) : mod(), bailout(_bailout), vc() {
+		vc.commandArgs(argc, argv);
+		vc.traceEverOn(true);
 		mod.clk = 0;
 		tick_count = 0;
 	}
@@ -19,10 +25,10 @@ template <class TOP> class TB {
 	virtual void run_clock() {
 		mod.clk = !mod.clk;
 		mod.eval();
-		Verilated::timeInc(1);
+		vc.timeInc(1);
 		mod.clk = !mod.clk;
 		mod.eval();
-		Verilated::timeInc(1);
+		vc.timeInc(1);
 		tick_count++;
 
 		if (bailout > 0 && tick_count >= bailout)