add clean.sh, add adc and dac pins to SOC properly
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98ee6cdecc
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145
soc.py
145
soc.py
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@ -35,36 +35,135 @@ from migen import *
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import litex_boards.platforms.digilent_arty as board_spec
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.integration.builder import Builder
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from litex.build.generic_platform import IOStandard, Pins
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from litex.build.generic_platform import IOStandard, Pins, Subsignal
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.interconnect.csr import AutoCSR, Module, CSRStorage, CSRStatus
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# Refer to `A7-constraints.xdc` for pin names.
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# SS MOSI MISO SCK
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# IO with Subsignals make Record types, which have the name of the
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# subsignal as an attribute.
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io = [
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("dac0", 0, Pins("G13 B11 A11 D12"), IOStandard("LVCMOS33")),
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("dac1", 0, Pins("D13 B18 A18 K16"), IOStandard("LVCMOS33")),
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("dac2", 0, Pins("E15 E16 D15 C15"), IOStandard("LVCMOS33")),
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("dac3", 0, Pins("J17 J18 K15 J15"), IOStandard("LVCMOS33")),
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("dac4", 0, Pins("U12 V12 V10 V11"), IOStandard("LVCMOS33")),
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("dac5", 0, Pins("U14 V14 T13 U13"), IOStandard("LVCMOS33")),
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("dac6", 0, Pins("D4 D3 F4 F3"), IOStandard("LVCMOS33")),
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("dac7", 0, Pins("E2 D2 H2 G2"), IOStandard("LVCMOS33")),
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("dac", 0,
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Subsignal("ss", Pins("G13")),
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Subsignal("mosi", Pins("B11")),
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Subsignal("miso", Pins("A11")),
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Subsignal("sck", Pins("D12")),
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IOStandard("LVCMOS33")),
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("dac", 1,
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Subsignal("ss", Pins("D13")),
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Subsignal("mosi", Pins("B18")),
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Subsignal("miso", Pins("A18")),
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Subsignal("sck", Pins("K16")),
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IOStandard("LVCMOS33")),
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("dac", 2,
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Subsignal("ss", Pins("E15")),
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Subsignal("mosi", Pins("E16")),
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Subsignal("miso", Pins("D15")),
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Subsignal("sck", Pins("C15")),
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IOStandard("LVCMOS33")),
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("dac", 3,
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Subsignal("ss", Pins("J17")),
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Subsignal("mosi", Pins("J18")),
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Subsignal("miso", Pins("K15")),
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Subsignal("sck", Pins("J15")),
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IOStandard("LVCMOS33")),
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("dac", 4,
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Subsignal("ss", Pins("U12")),
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Subsignal("mosi", Pins("V12")),
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Subsignal("miso", Pins("V10")),
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Subsignal("sck", Pins("V11")),
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IOStandard("LVCMOS33")),
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("dac", 5,
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Subsignal("ss", Pins("U14")),
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Subsignal("mosi", Pins("V14")),
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Subsignal("miso", Pins("T13")),
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Subsignal("sck", Pins("U13")),
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IOStandard("LVCMOS33")),
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("dac", 6,
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Subsignal("ss", Pins("D4")),
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Subsignal("mosi", Pins("D3")),
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Subsignal("miso", Pins("F4")),
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Subsignal("sck", Pins("F3")),
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IOStandard("LVCMOS33")),
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("dac", 7,
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Subsignal("ss", Pins("E2")),
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Subsignal("mosi", Pins("D2")),
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Subsignal("miso", Pins("H2")),
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Subsignal("sck", Pins("G2")),
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IOStandard("LVCMOS33")),
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("adc0", 0, Pins("V15 U16 P14"), IOStandard("LVCMOS33")),
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("adc1", 0, Pins("T11 R12 T14"), IOStandard("LVCMOS33")),
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("adc2", 0, Pins("T15 T16 N15"), IOStandard("LVCMOS33")),
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("adc3", 0, Pins("M16 V17 U18"), IOStandard("LVCMOS33")),
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("adc4", 0, Pins("U11 V16 M13"), IOStandard("LVCMOS33")),
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("adc5", 0, Pins("R10 R11 R13"), IOStandard("LVCMOS33")),
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("adc6", 0, Pins("R15 P15 R16"), IOStandard("LVCMOS33")),
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("adc7", 0, Pins("N16 N14 U17"), IOStandard("LVCMOS33"))
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("adc", 0,
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Subsignal("conv", Pins("V15")),
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Subsignal("sck", Pins("U16")),
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Subsignal("sdo", Pins("P14")),
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IOStandard("LVCMOS33")),
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("adc", 1,
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Subsignal("conv", Pins("T11")),
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Subsignal("sck", Pins("R12")),
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Subsignal("sdo", Pins("T14")),
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IOStandard("LVCMOS33")),
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("adc", 2,
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Subsignal("conv", Pins("T15")),
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Subsignal("sck", Pins("T16")),
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Subsignal("sdo", Pins("N15")),
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IOStandard("LVCMOS33")),
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("adc", 3,
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Subsignal("conv", Pins("M16")),
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Subsignal("sck", Pins("V17")),
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Subsignal("sdo", Pins("U18")),
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IOStandard("LVCMOS33")),
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("adc", 4,
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Subsignal("conv", Pins("U11")),
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Subsignal("sck", Pins("V16")),
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Subsignal("sdo", Pins("M13")),
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IOStandard("LVCMOS33")),
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("adc", 5,
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Subsignal("conv", Pins("R10")),
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Subsignal("sck", Pins("R11")),
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Subsignal("sdo", Pins("R13")),
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IOStandard("LVCMOS33")),
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("adc", 6,
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Subsignal("conv", Pins("R15")),
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Subsignal("sck", Pins("P15")),
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Subsignal("sdo", Pins("R16")),
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IOStandard("LVCMOS33")),
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("adc", 7,
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Subsignal("conv", Pins("N16")),
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Subsignal("sck", Pins("N14")),
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Subsignal("sdo", Pins("U17")),
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IOStandard("LVCMOS33"))
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]
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class DACThroughGPIO(Module, AutoCSR):
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def __init__(self, pins):
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self._ss = CSRStorage(1, description="Slave Select (Control)")
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self._mosi = CSRStorage(1, description="Master Out, Slave In (Control)")
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self._miso = CSRStatus(1, description="Master In, Slave Out (Status)")
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self._sck = CSRStorage(1, description="Serial Clock (Control)")
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self._pins = pins
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self.comb += self._pins.ss.eq(self._ss.storage)
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self.comb += self._pins.mosi.eq(self._mosi.storage)
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self.comb += self._pins.sck.eq(self._sck.storage)
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self.comb += self._miso.status.eq(self._pins.miso)
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class ADCThroughGPIO(Module, AutoCSR):
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def __init__(self, pins):
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self._pins = pins
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self._conv = CSRStorage(1, description="Conversion Signal (Control)")
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self._sck = CSRStorage(1, description="Serial Clock (Control)")
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self._sdo = CSRStatus(1, description="Serial Data Output (Status)")
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self.comb += self._pins.conv.eq(self._conv.storage)
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self.comb += self._pins.sck.eq(self._sck.storage)
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self.comb += self._sdo.status.eq(self._pins.sdo)
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_rst=True):
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self.rst = Signal()
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@ -75,9 +174,6 @@ class _CRG(Module):
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self.clock_domains.cd_sys4x_dqs = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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# Clk/Rst.
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clk100 = platform.request("clk100")
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rst = ~platform.request("cpu_reset") if with_rst else 0
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@ -141,10 +237,9 @@ class CryoSNOM1SoC(SoCCore):
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# Add the DAC and ADC pins as GPIO. They will be used directly
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# by Zephyr.
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platform.add_extension(io)
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for name in [f"dac{n}" for n in range(0,8)]:
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setattr(self.submodules, name, GPIOTristate(platform.request(name)))
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for name in [f"adc{n}" for n in range(0,8)]:
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setattr(self.submodules, name, GPIOTristate(platform.request(name)))
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for i in range(0,8):
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setattr(self.submodules, f"dac{i}", DACThroughGPIO(platform.request("dac", i)))
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setattr(self.submodules, f"adc{i}", ADCThroughGPIO(platform.request("adc", i)))
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def main():
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soc = CryoSNOM1SoC("a7-35")
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