refactor compiles
This commit is contained in:
parent
054609a459
commit
cf95a0fd20
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@ -49,7 +49,6 @@ hardware-get:
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docker cp upsilon-hardware:/home/user/upsilon/gateware/arty.dtb ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/mmio.py ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/csr.json ../boot/
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docker cp upsilon-hardware:/home/user/upsilon/gateware/csr_bitwidth.json ../boot/
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hardware-clean:
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-docker container stop upsilon-hardware
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-docker container rm upsilon-hardware
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@ -15,59 +15,23 @@ import collections
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import argparse
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import json
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import sys
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class MMIORegister:
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def __init__(self, name, read_only=False, number=1, exntype=None):
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"""
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Describes a MMIO register.
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:param name: The name of the MMIO register, excluding the prefix
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defining its module (i.e. ``base_``) and excluding its
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numerical suffix.
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:param read_only: True if the register is read only. Defaults to
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``False``.
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:param number: The number of MMIO registers with the same name
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and number suffixes. The number suffixes must go from 0
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to ``number - 1`` with no gaps.
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"""
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self.name = name
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self.read_only = read_only
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self.number = number
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self.exntype = exntype
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# These are filled in by the CSR file.
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self.size = None
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def mmio_factory(num, exntype):
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"""
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Return a function that simplifies the creation of instances of
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:py:class:`MMIORegister` with the same number and exception type.
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:param num: Number of registers with the same name (minus suffix).
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:param exntype: MicroPython exception type.
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:return: A function ``f(name, read_only=False)``. Each argument is
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the same as the one in the initializer of py:class:`MMIORegister`.
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"""
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def f(name, read_only=False):
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return MMIORegister(name, read_only, number=num, exntype=exntype)
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return f
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import mmio_descr
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class CSRHandler:
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"""
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Class that wraps the CSR file and fills in registers with information
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from those files.
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"""
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def __init__(self, csrjson, bitwidthjson, registers):
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def __init__(self, csrjson, registers):
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"""
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Reads in the CSR files.
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:param csrjson: Filename of a LiteX "csr.json" file.
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:param bitwidthjson: Filename of an Upsilon "bitwidthjson" file.
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:param registers: A list of :py:class:`MMIORegister`s.
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:param registers: A list of ``mmio_descr`` ``Descr``s.
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:param outf: Output file.
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"""
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self.registers = registers
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self.csrs = json.load(open(csrjson))
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self.bws = json.load(open(bitwidthjson))
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def update_reg(self, reg):
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"""
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@ -76,17 +40,19 @@ class CSRHandler:
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:param reg: The register.
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:raises Exception: When the bit width exceeds 64.
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"""
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b = self.bws[reg.name]
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regsize = None
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b = reg.blen
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if b <= 8:
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reg.size = 8
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regsize = 8
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elif b <= 16:
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reg.size = 16
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regsize = 16
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elif b <= 32:
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reg.size = 32
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regsize = 32
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elif b <= 64:
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reg.size = 64
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regsize = 64
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else:
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raise Exception(f"unsupported width {b} in {reg.name}")
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setattr(reg, "regsize", regsize)
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def get_reg_addr(self, reg, num=None):
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"""
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@ -135,7 +101,7 @@ class InterfaceGenerator:
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self.print(self.header())
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for r in self.csr.registers:
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self.print(self.fun(r, "read"))
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if not r.read_only:
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if not r.rwperm != "read-only":
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self.print(self.fun(r, "write"))
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class MicropythonGenerator(InterfaceGenerator):
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@ -144,9 +110,9 @@ class MicropythonGenerator(InterfaceGenerator):
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def get_accessor(self, reg, num):
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addr = self.csr.get_reg_addr(reg, num)
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if reg.size in [8, 16, 32]:
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return [f"machine.mem{reg.size}[{addr}]"]
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return [f"machine.mem32[{addr}]", f"machine.mem32[{addr + 4}]"]
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if reg.regsize in [8, 16, 32]:
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return [f"machine.mem{reg.regsize}[{addr}]"]
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return [f"machine.mem32[{addr + 4}]", f"machine.mem32[{addr}]"]
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def print_write_register(self, indent, varname, reg, num):
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acc = self.get_accessor(reg, num)
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@ -181,16 +147,16 @@ class MicropythonGenerator(InterfaceGenerator):
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else:
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pfun = self.print_read_register
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if reg.number != 1:
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if reg.num != 1:
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if printed_argument:
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a(', ')
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a('num')
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a('):\n')
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if reg.number == 1:
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if reg.num == 1:
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a(pfun('\t', 'val', reg, None))
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else:
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for i in range(0,reg.number):
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for i in range(0,reg.num):
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if i == 0:
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a(f'\tif ')
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else:
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@ -198,46 +164,16 @@ class MicropythonGenerator(InterfaceGenerator):
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a(f'num == {i}:\n')
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a(pfun('\t\t', 'val', reg, i))
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a(f'\telse:\n')
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a(f'\t\traise {r.exntype}(regnum)\n')
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a(f'\t\traise Exception(regnum)\n')
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a('\n')
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return rs
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def header(self):
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return """import machine
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class InvalidDACException(Exception):
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pass
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class InvalidADCException(Exception):
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pass
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"""
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return "import machine\n"
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if __name__ == "__main__":
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dac_num = 8
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adc_num = 8
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dac_reg = mmio_factory(dac_num, "InvalidDACException")
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adc_reg = mmio_factory(adc_num, "InvalidADCException")
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registers = [
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dac_reg("dac_sel"),
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dac_reg("dac_finished", read_only=True),
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dac_reg("dac_arm"),
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dac_reg("dac_recv_buf", read_only=True),
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dac_reg("dac_send_buf"),
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adc_reg("adc_finished", read_only=True),
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adc_reg("adc_arm"),
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adc_reg("adc_recv_buf", read_only=True),
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adc_reg("adc_sel"),
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MMIORegister("cl_in_loop", read_only=True),
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MMIORegister("cl_cmd"),
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MMIORegister("cl_word_in"),
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MMIORegister("cl_word_out", read_only=True),
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MMIORegister("cl_start_cmd"),
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MMIORegister("cl_finish_cmd", read_only=True),
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MMIORegister("cl_z_report", read_only=True),
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]
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csrh = CSRHandler(sys.argv[1], sys.argv[2], registers)
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for r in registers:
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csrh = CSRHandler(sys.argv[1], mmio_descr.registers)
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for r in mmio_descr.registers:
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csrh.update_reg(r)
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MicropythonGenerator(csrh, sys.stdout).print_file()
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@ -11,15 +11,15 @@ class Descr:
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"""
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self.name = name
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self.blen = blen
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self.doc = textwrap.deindent(descr)
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self.doc = textwrap.dedent(descr)
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self.num =num
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self.read_only = read_only == "read-only"
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self.rwperm = rwperm
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@classmethod
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def from_dict(cls, jsdict, name):
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return cls(name, jsdict[name]["len"], jsdict[name]["ro"], jsdict[name]["num"], jsdict[name]["doc"])
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def store_to_dict(self, d):
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d[self.name = {
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d[self.name] = {
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"len": self.blen,
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"doc": self.doc,
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"num": self.num,
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@ -27,7 +27,7 @@ class Descr:
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}
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registers = [
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Descr("adc_sel", 3, "read-write", """\
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Descr("adc_sel", 3, "read-write", 8, """\
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Select which on-FPGA SPI master controls the ADC.
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Valid settings:
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@ -36,7 +36,7 @@ registers = [
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* ``0b10``: ADC is controlled by MMIO registers, but conversion is
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disabled. This is used to flush output from an out-of-sync ADC.
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* ``0b100``: ADC 0 only. ADC is controlled by control loop."""),
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Descr("adc_finished", "read-only", """\
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Descr("adc_finished", 1, "read-only", 8, """\
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Signals that an ADC master has finished an SPI cycle.
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Values:
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@ -47,9 +47,8 @@ registers = [
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This flag is on only when ``adc_arm`` is high. The flag does not
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mean that data has been received successfully, only that the master
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has finished it's SPI transfer.
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"""),
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Descr("adc_arm", "read-write", """\
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has finished it's SPI transfer."""),
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Descr("adc_arm", 1, "read-write", 8, """\
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Start a DAC master SPI transfer.
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If ``adc_arm`` is raised from and the master is currently not in a SPI
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@ -84,7 +83,7 @@ registers = [
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If ``adc_sel`` is not set to 0 then the transfer will proceed
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as normal, but no data will be received from the ADC."""),
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Descr("adc_recv_buf", "read-only", """\
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Descr("adc_recv_buf", 18, "read-only", 8, """\
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ADC Master receive buffer.
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This buffer is stable if there is no ADC transfer caused by ``adc_arm``
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@ -94,14 +93,14 @@ registers = [
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registers. SPI transfers by other masters will not affect this register.
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buffer."""),
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Descr("dac_sel", 2, "read-write", """\
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Descr("dac_sel", 2, "read-write", 8, """\
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Select which on-FPGA SPI master controls the DAC.
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Valid settings:
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* ``0``: DAC is controlled by MMIO registers.
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* ``0b10``: DAC 0 only. DAC is controlled by control loop."""),
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Descr("dac_finished", 1, "read-only", """\
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Descr("dac_finished", 1, "read-only", 8, """\
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Signals that the DAC master has finished transmitting data.
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Values:
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@ -113,7 +112,7 @@ registers = [
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This flag is on only when ``dac_arm`` is high. The flag does not
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mean that data has been received or transmitted successfully, only that
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the master has finished it's SPI transfer."""),
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Descr("dac_arm", 1, "read-write", """\
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Descr("dac_arm", 1, "read-write", 8, """\
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Start a DAC master SPI transfer.
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If ``dac_arm`` is raised from and the master is currently not in a SPI
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@ -138,7 +137,7 @@ registers = [
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If ``dac_sel`` is set to another master then the transfer will proceed
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as normal, but no data will be sent to or received from the DAC."""),
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Descr("dac_recv_buf", 24, "read-only", """\
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Descr("dac_recv_buf", 24, "read-only", 8, """\
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DAC master receive buffer.
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This buffer is stable if there is no DAC transfer caused by ``dac_arm``
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@ -147,7 +146,7 @@ registers = [
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This register only changes if an SPI transfer is triggered by the MMIO
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registers. SPI transfers by other masters will not affect this register.
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buffer."""),
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Descr("dac_send_buf, 24, "read-write", """\
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Descr("dac_send_buf", 24, "read-write", 8, """\
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DAC master send buffer.
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Fill this buffer with a 24 bit Analog Devices DAC command. Updating
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@ -158,7 +157,7 @@ registers = [
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Modifying this buffer during a transfer does not disrupt an in-process
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transfer."""),
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Descr("cl_assert_change", 1, "read-write", """\
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Descr("cl_assert_change", 1, "read-write", 1, """\
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Flush parameter changes to control loop.
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When this bit is raised from low to high, this signals the control
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@ -168,21 +167,23 @@ registers = [
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When this bit is raised from high to low before ``cl_change_made``
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is asserted by the control loop, nothing happens."""),
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Descr("cl_change_made", 1, "read-only", """\
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Descr("cl_change_made", 1, "read-only", 1, """\
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Signal from the control loop that the parameters have been applied.
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This signal goes high only while ``cl_assert_change`` is high. No
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change will be applied afterwards while both are high."""),
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Descr("cl_in_loop_in", 1, "read-only", """\
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Descr("cl_in_loop", 1, "read-only", 1, """\
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This bit is high if the control loop is running."""),
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Descr("cl_setpt_in", 18, "read-write", """\
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Descr("cl_run_loop_in", 1, "read-write", 1, """\
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Set this bit high to start the control loop."""),
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Descr("cl_setpt_in", 18, "read-write", 1, """\
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Setpoint of the control loop.
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This is a twos-complement number in ADC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_P_in", 64, "read-write", """\
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Descr("cl_P_in", 64, "read-write", 1, """\
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Proportional parameter of the control loop.
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This is a twos-complement fixed point number with 21 whole
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@ -190,7 +191,7 @@ registers = [
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in DAC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_I_in", 64, "read-write", """\
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Descr("cl_I_in", 64, "read-write", 1, """\
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Integral parameter of the control loop.
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This is a twos-complement fixed point number with 21 whole
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@ -198,7 +199,7 @@ registers = [
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in DAC units.
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_delay_in", 16, "read-write", """\
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Descr("cl_delay_in", 16, "read-write", 1, """\
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Delay parameter of the loop.
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This is an unsigned number denoting the number of cycles
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@ -206,15 +207,15 @@ registers = [
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This is a parameter: see ``cl_assert_change``."""),
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Descr("cl_cycle_count", 18, "read-only", """\
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Descr("cl_cycle_count", 18, "read-only", 1, """\
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Delay parameter of the loop.
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This is an unsigned number denoting the number of cycles
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the loop should wait between loop executions."""),
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Descr("cl_z_pos", 20, "read-only", """\
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Descr("cl_z_pos", 20, "read-only", 1, """\
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Control loop DAC Z position.
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"""),
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Descr("cl_z_measured", 18, "read-only", """\
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Descr("cl_z_measured", 18, "read-only", 1, """\
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Control loop ADC Z position.
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"""),
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]
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@ -292,6 +292,7 @@ m4_define(CL_DATA_WID, CL_CONSTS_WID)
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input cl_assert_change,
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output cl_change_made,
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output cl_in_loop,
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input cl_run_loop_in,
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input [ADC_TYPE1_WID-1:0] cl_setpt_in,
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@ -299,9 +300,9 @@ m4_define(CL_DATA_WID, CL_CONSTS_WID)
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input [CL_DATA_WID-1:0] cl_I_in,
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input [CL_DELAY_WID-1:0] cl_delay_in,
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output [CYCLE_COUNT_WID-1:0] cl_cycle_count,
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output [CL_CYCLE_COUNT_WID-1:0] cl_cycle_count,
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output [DAC_DATA_WID-1:0] cl_z_pos,
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output [ADC_WID-1:0] cl_z_measured
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output [ADC_TYPE1_WID-1:0] cl_z_measured
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);
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assign set_low = 0;
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@ -144,7 +144,7 @@ class Base(Module, AutoCSR):
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if num is not None:
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name = f"{name}_{num}"
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if self.ro == "read-only":
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if reg.rwperm == "read-only":
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csrclass = CSRStatus
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else:
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csrclass = CSRStorage
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