From cfb0f92528b7b4c38405b63d4a80135e183a314b Mon Sep 17 00:00:00 2001 From: Peter McGoron Date: Mon, 21 Nov 2022 22:04:46 -0500 Subject: [PATCH] fix adc_sim --- firmware/rtl/control_loop/adc_sim.v | 2 +- firmware/rtl/control_loop/control_loop.v | 2 +- firmware/rtl/control_loop/control_loop_sim.cpp | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/firmware/rtl/control_loop/adc_sim.v b/firmware/rtl/control_loop/adc_sim.v index 1806a97..c115a4a 100644 --- a/firmware/rtl/control_loop/adc_sim.v +++ b/firmware/rtl/control_loop/adc_sim.v @@ -39,8 +39,8 @@ always @ (posedge clk) begin data <= indat; fulfilled_raised <= 1; request <= 0; - end else if (ss_raised && request && !fulfilled && fulfilled_raised) begin rdy <= 1; + end else if (ss_raised && !fulfilled && fulfilled_raised) begin fulfilled_raised <= 0; ss_buf_L <= 0; end else if (spi_fin) begin diff --git a/firmware/rtl/control_loop/control_loop.v b/firmware/rtl/control_loop/control_loop.v index c7dfc1a..a6d23c0 100644 --- a/firmware/rtl/control_loop/control_loop.v +++ b/firmware/rtl/control_loop/control_loop.v @@ -226,7 +226,7 @@ reg [DELAY_WID-1:0] timer = 0; /**** Timing. ****/ always @ (posedge clk) begin - if (state == CYCLE_START) begin + if (state == CYCLE_START && timer == 0) begin counting_timer <= 1; last_timer <= counting_timer; end else begin diff --git a/firmware/rtl/control_loop/control_loop_sim.cpp b/firmware/rtl/control_loop/control_loop_sim.cpp index bac4362..6c6ac37 100644 --- a/firmware/rtl/control_loop/control_loop_sim.cpp +++ b/firmware/rtl/control_loop/control_loop_sim.cpp @@ -56,6 +56,7 @@ int main(int argc, char **argv) { set_value(0b11010111000010100011110101110000101000111, CONTROL_LOOP_P); set_value((V)12 << CONSTS_FRAC, CONTROL_LOOP_I); set_value(20, CONTROL_LOOP_DELAY); + set_value(10000, CONTROL_LOOP_SETPT); set_value(1, CONTROL_LOOP_STATUS); for (int tick = 0; tick < 10000; tick++) {