move SPI master out of control loop design
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@ -1,4 +1,5 @@
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/* TODO: move SPI masters out of the control loop design */
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/* TODO: standardised access that isn't ad-hoc: wishbone
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* bus */
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/************ Introduction to PI Controllers
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/************ Introduction to PI Controllers
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* The continuous form of a PI loop is
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* The continuous form of a PI loop is
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@ -128,20 +129,20 @@ module control_loop
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) (
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) (
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input clk,
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input clk,
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input arm,
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input arm,
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output running,
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output adc_sck,
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input signed [ADC_WID-1:0] measured_value,
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input adc_in,
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output adc_conv,
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output adc_conv, // active high
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output adc_arm,
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input adc_finished,
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output dac_sck,
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output signed [DAC_WID-1:0] to_dac,
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output dac_ss, // active high
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output dac_ss,
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output dac_out,
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output dac_arm,
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input dac_finished
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/* Informational output.
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* These registers are also used for storing information while
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* the loop is running.
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*/
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input reg read_err_cur,
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output reg read_err_cur_finished,
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output signed [ERR_WID-1:0] err_cur,
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output signed [ERR_WID-1:0] err_cur,
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output signed [CONSTS_WID-1:0] adj,
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output signed [CONSTS_WID-1:0] adj,
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@ -220,28 +221,8 @@ reg [STATESIZ-1:0] state = WAIT_ON_ARM;
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* --> reinterpret and write into DAC: DAC_DATA_WID.0
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* --> reinterpret and write into DAC: DAC_DATA_WID.0
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*/
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*/
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/******* Get measured value ********/
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reg signed [ADC_WID-1:0] measured = 0;
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reg adc_arm = 0;
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wire adc_finished;
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spi_master_no_write #(
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.WID(ADC_WID),
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.POLARITY(ADC_POLARITY),
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.PHASE(ADC_PHASE),
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.CYCLE_HALF_WAIT(1),
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.TIMER_LEN(3)
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) adc (
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.clk(clk),
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.from_slave(adcbuf),
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.miso(adc_in),
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.sck_wire(adc_sck),
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.arm(adc_arm),
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.finished(adc_finished)
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);
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/**** Calculate Error ****/
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/**** Calculate Error ****/
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assign err_cur = measured - setpoint;
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assign err_cur = measured_value - setpoint;
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/****** Multiplication *******
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/****** Multiplication *******
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* Truncation of a fixed-point integer to a smaller buffer requires
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* Truncation of a fixed-point integer to a smaller buffer requires
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@ -268,7 +249,7 @@ wire signed [MUL_WID-1:0] alpha_err;
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wire p_err_prev_fin;
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wire p_err_prev_fin;
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wire signed [MUL_WID-1:0] p_err_prev;
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wire signed [MUL_WID-1:0] p_err_prev;
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wire mul_finished = alpha_err_prev_fin & p_err_fin;
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wire mul_finished = alpha_err_fin & p_err_fin;
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/* αe */
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/* αe */
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boothmul #(
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boothmul #(
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@ -334,28 +315,14 @@ wire signed dac_adj_val[DAC_DATA_WID-1:0];
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intsat #(
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intsat #(
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.IN_LEN(RTRUNC_WID),
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.IN_LEN(RTRUNC_WID),
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.LTRUNC(DAC_DATA_WID)
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.LTRUNC(DAC_DATA_WID)
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) (
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) sat_newadj_rtrunc (
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.inp(newadj_rtrunc),
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.inp(newadj_rtrunc),
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.outp(dac_adj_val)
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.outp(dac_adj_val)
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);
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);
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/**** Write to DAC ****/
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/**** Write to DAC ****/
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reg dac_arm = 0;
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assign to_dac = {4'b0010,dac_adj_val};
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spi_master_no_read #(
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.WID(DAC_WID),
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.WID_LEN(5),
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.CYCLE_HALF_WAIT(3),
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.TIMER_LEN(3),
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.POLARITY(DAC_POLARITY),
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.PHASE(DAC_PHASE)
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) dac (
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.clk(clk),
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.to_slave({4'b0010,dac_adj_val}),
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.mosi(dac_out),
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.sck_wire(dac_sck),
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.arm(dac_arm)
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);
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reg [DELAY_WID-1:0] timer = 0;
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reg [DELAY_WID-1:0] timer = 0;
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@ -366,14 +333,19 @@ always @ (posedge clk) begin
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adj_prev <= 0;
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adj_prev <= 0;
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err_prev <= 0;
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err_prev <= 0;
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timer <= 0;
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timer <= 0;
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running <= 0;
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end else if (timer == 0) begin
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end else if (timer == 0) begin
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saved_delay <= delay_in;
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saved_delay <= delay_in;
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timer <= 1;
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timer <= 1;
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running <= 1;
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setpt <= setpt_in;
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/* TODO: cl_alpha change only when loop is stopped */
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cl_alpha_reg <= cl_alpha_in;
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cl_p_reg <= cl_p_in;
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state <= WAIT_LOOP_DELAY;
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end else if (timer < saved_delay) begin
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end else if (timer < saved_delay) begin
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timer <= timer + 1;
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timer <= timer + 1;
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setpt <= setpt_in;
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setpt <= setpt_in;
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cl_alpha_reg <= cl_alpha_in;
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cl_p_reg <= cl_p_in;
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end else begin
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end else begin
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state <= WAIT_ON_ADC;
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state <= WAIT_ON_ADC;
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timer <= 0;
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timer <= 0;
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